Versions in this module Expand all Collapse all v0 v0.1.3 Oct 15, 2025 Changes in this version type Master + func (d *Master) DMAISR() v0.1.2 Oct 13, 2025 Changes in this version + const ABORTn + const ABRT_10ADDR1_NOACKn + const ABRT_10ADDR2_NOACKn + const ABRT_10B_RD_NORSTRTn + const ABRT_7B_ADDR_NOACKn + const ABRT_GCALL_NOACKn + const ABRT_GCALL_READn + const ABRT_HS_ACKDETn + const ABRT_HS_NORSTRTn + const ABRT_MASTER_DISn + const ABRT_SBYTE_ACKDETn + const ABRT_SBYTE_NORSTRTn + const ABRT_SLVFLUSH_TXFIFOn + const ABRT_SLVRD_INTXn + const ABRT_SLV_ARBLOSTn + const ABRT_TXDATA_NOACKn + const ABRT_USER_ABRTn + const ACK_GEN_CALLn + const ACTIVITYn + const ACTn + const ADDRn + const ADD_ENCODED_PARAMSn + const APB_DATA_WIDTHn + const ARB_LOSTn + const CMD + const CMDn + const DAT + const DATn + const ENABLEDn + const ENn + const FIRST_DATA_BYTE + const FIRST_DATA_BYTEn + const GC_OR_STARTn + const GEN_CALLn + const HAS_DMAn + const HC_COUNT_VALUESn + const INTR_IOn + const MASTER_10BITADDRn + const MASTER_MODEn + const MAX_SPEED_MODEn + const MST_ACTn + const NACKn + const RDMAEn + const RD_REQn + const RESTART + const RESTART_DETn + const RESTART_ENn + const RESTARTn + const RFFn + const RFNEn + const RX_BUFFER_DEPTHn + const RX_DONEn + const RX_FIFO_FULL_HLD_CTRLn + const RX_FULLn + const RX_OVERn + const RX_UNDERn + const Recv + const Restart + const SDA_RX_HOLDn + const SDA_TX_HOLDn + const SLAVE_10BITADDRn + const SLAVE_DISABLEn + const SLV_ACTn + const SLV_DISABLED_WHILE_BUSYn + const SLV_RX_DATA_LOSTn + const SPECIALn + const SPEEDn + const START_DETn + const STOP + const STOP_DET_IFADDRESSEDn + const STOP_DET_IF_MASTER_ACTIVEn + const STOP_DETn + const STOPn + const Send + const Stop + const TDMAEn + const TFEn + const TFNFn + const TX_ABRTn + const TX_BUFFER_DEPTHn + const TX_CMD_BLOCKn + const TX_EMPTY_CTRLn + const TX_EMPTYn + const TX_FLUSH_CNTn + const TX_OVERn + type ACK_GENERAL_CALL uint32 + const ACK_GEN_CALL + type COMP_PARAM_1 uint32 + const ADD_ENCODED_PARAMS + const APB_DATA_WIDTH + const HAS_DMA + const HC_COUNT_VALUES + const INTR_IO + const MAX_SPEED_MODE + const RX_BUFFER_DEPTH + const TX_BUFFER_DEPTH + type CON uint32 + const FAST + const HIGH + const MASTER_10BITADDR + const MASTER_MODE + const RESTART_EN + const RX_FIFO_FULL_HLD_CTRL + const SLAVE_10BITADDR + const SLAVE_DISABLE + const SPEED + const STANDARD + const STOP_DET_IFADDRESSED + const STOP_DET_IF_MASTER_ACTIVE + const TX_EMPTY_CTRL + type DMA_CR uint32 + const RDMAE + const TDMAE + type ENABLE uint32 + const ABORT + const EN + const TX_CMD_BLOCK + type ENABLE_STATUS uint32 + const ENABLED + const SLV_DISABLED_WHILE_BUSY + const SLV_RX_DATA_LOST + type INTR uint32 + const ACTIVITY + const GEN_CALL + const RD_REQ + const RESTART_DET + const RX_DONE + const RX_FULL + const RX_OVER + const RX_UNDER + const START_DET + const STOP_DET + const TX_ABRT + const TX_EMPTY + const TX_OVER + type Master struct + func NewMaster(p *Periph, dma dma.Channel) *Master + func (d *Master) Abort() + func (d *Master) Clear(flags INTR) + func (d *Master) Err(clear bool) (err error) + func (d *Master) Flush() + func (d *Master) ID() uint8 + func (d *Master) ISR() + func (d *Master) Name() string + func (d *Master) NewConn(a i2cbus.Addr) i2cbus.Conn + func (d *Master) Periph() *Periph + func (d *Master) ReadByte() (b byte) + func (d *Master) ReadBytes(p []byte) + func (d *Master) SetAddr(addr i2cbus.Addr) + func (d *Master) SetID(id uint8) + func (d *Master) SetName(s string) + func (d *Master) Setup(baudrate int) + func (d *Master) Status() INTR + func (d *Master) UsePin(pin iomux.Pin, sig Signal) bool + func (d *Master) Wait(flags INTR) + func (d *Master) WriteBytes(p []byte) + func (d *Master) WriteCmd(cmd int16) + func (d *Master) WriteCmds(cmds []int16) + func (d *Master) WriteStr(s string) + type MasterError struct + Abort TX_ABRT_SOURCE + Bus string + func (e *MasterError) Error() string + func (e *MasterError) Is(target error) bool + type Periph struct + ACK_GENERAL_CALL mmio.R32[ACK_GENERAL_CALL] + CLR_ACTIVITY mmio.U32 + CLR_GEN_CALL mmio.U32 + CLR_INTR mmio.U32 + CLR_RD_REQ mmio.U32 + CLR_RESTART_DET mmio.U32 + CLR_RX_DONE mmio.U32 + CLR_RX_OVER mmio.U32 + CLR_RX_UNDER mmio.U32 + CLR_START_DET mmio.U32 + CLR_STOP_DET mmio.U32 + CLR_TX_ABRT mmio.U32 + CLR_TX_OVER mmio.U32 + COMP_PARAM_1 mmio.R32[COMP_PARAM_1] + COMP_TYPE mmio.U32 + COMP_VERSION mmio.U32 + CON mmio.R32[CON] + DATA_CMD mmio.U32 + DMA_CR mmio.R32[DMA_CR] + DMA_RDLR mmio.U32 + DMA_TDLR mmio.U32 + ENABLE mmio.R32[ENABLE] + ENABLE_STATUS mmio.R32[ENABLE_STATUS] + FS_SCL_HCNT mmio.U32 + FS_SCL_LCNT mmio.U32 + FS_SPKLEN mmio.U32 + INTR_MASK mmio.R32[INTR] + INTR_STAT mmio.R32[INTR] + RAW_INTR_STAT mmio.R32[INTR] + RXFLR mmio.U32 + RX_TL mmio.U32 + SAR mmio.U32 + SDA_HOLD mmio.R32[SDA_HOLD] + SDA_SETUP mmio.U32 + SLV_DATA_NACK_ONLY mmio.R32[SLV_DATA_NACK_ONLY] + SS_SCL_HCNT mmio.U32 + SS_SCL_LCNT mmio.U32 + STATUS mmio.R32[STATUS] + TAR mmio.R32[TAR] + TXFLR mmio.U32 + TX_ABRT_SOURCE mmio.R32[TX_ABRT_SOURCE] + TX_TL mmio.U32 + func I2C(n int) *Periph + func (p *Periph) Pins(sig Signal) []iomux.Pin + func (p *Periph) SetReset(assert bool) + type SDA_HOLD uint32 + const SDA_RX_HOLD + const SDA_TX_HOLD + type SLV_DATA_NACK_ONLY uint32 + const NACK + type STATUS uint32 + const ACT + const MST_ACT + const RFF + const RFNE + const SLV_ACT + const TFE + const TFNF + type Signal int8 + const SCL + const SDA + type TAR uint32 + const ADDR + const GC_OR_START + const SPECIAL + type TX_ABRT_SOURCE uint32 + const ABRT_10ADDR1_NOACK + const ABRT_10ADDR2_NOACK + const ABRT_10B_RD_NORSTRT + const ABRT_7B_ADDR_NOACK + const ABRT_GCALL_NOACK + const ABRT_GCALL_READ + const ABRT_HS_ACKDET + const ABRT_HS_NORSTRT + const ABRT_MASTER_DIS + const ABRT_SBYTE_ACKDET + const ABRT_SBYTE_NORSTRT + const ABRT_SLVFLUSH_TXFIFO + const ABRT_SLVRD_INTX + const ABRT_SLV_ARBLOST + const ABRT_TXDATA_NOACK + const ABRT_USER_ABRT + const ARB_LOST + const TX_FLUSH_CNT
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