micro

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Overview

Copyright Consensys Software Inc.

Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

SPDX-License-Identifier: Apache-2.0

Copyright Consensys Software Inc.

Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

SPDX-License-Identifier: Apache-2.0

Copyright Consensys Software Inc.

Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

SPDX-License-Identifier: Apache-2.0

Copyright Consensys Software Inc.

Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

SPDX-License-Identifier: Apache-2.0

Copyright Consensys Software Inc.

Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

SPDX-License-Identifier: Apache-2.0

Copyright Consensys Software Inc.

Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

SPDX-License-Identifier: Apache-2.0

Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

SPDX-License-Identifier: Apache-2.0

Copyright Consensys Software Inc.

Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

SPDX-License-Identifier: Apache-2.0

Copyright Consensys Software Inc.

Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

SPDX-License-Identifier: Apache-2.0

Copyright Consensys Software Inc.

Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

SPDX-License-Identifier: Apache-2.0

Copyright Consensys Software Inc.

Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

SPDX-License-Identifier: Apache-2.0

Copyright Consensys Software Inc.

Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

SPDX-License-Identifier: Apache-2.0

Copyright Consensys Software Inc.

Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

SPDX-License-Identifier: Apache-2.0

Index

Constants

This section is empty.

Variables

This section is empty.

Functions

This section is empty.

Types

type Assign 

type Assign struct {
	// Target registers for addition where the least significant come first.
	Targets []io.RegisterId
	// Source register for addition
	Source Polynomial
}

Assign represents a generic assignment of the following form:

tn, .., t0 := M0 + ... + Mm

Here, t0 .. tn are the *target registers*, of which tn is the *most significant*. These must be disjoint as we cannot assign simultaneously to the same register. In contrast, the right hand side represent a polynomial (i.e. the sum of m monomials). Observe that bitwidths represented by the left- and right-hand sides must match. For example, consider this case:

c, r0 := r1 + 1

Suppose that r0 and r1 are 16bit registers, whilst c is a 1bit register. The result of r1 + 1 occupies 17bits, of which the first 16 are written to r0 with the most significant (i.e. 16th) bit written to c. Thus, in this particular example, c represents a carry flag.

func (*Assign) Clone 

func (p *Assign) Clone() Code

Clone this micro code.

func (*Assign) MicroExecute 

func (p *Assign) MicroExecute(state io.State) (uint, uint)

MicroExecute a given micro-code, using a given state. This may update the register values, and returns either the number of micro-codes to "skip over" when executing the enclosing instruction or, if skip==0, a destination program counter (which can signal return of enclosing function).

func (*Assign) RegistersRead 

func (p *Assign) RegistersRead() []io.RegisterId

RegistersRead returns the set of registers read by this instruction.

func (*Assign) RegistersWritten 

func (p *Assign) RegistersWritten() []io.RegisterId

RegistersWritten returns the set of registers written by this instruction.

func (*Assign) Split 

func (p *Assign) Split(mapping register.LimbsMap, env agnostic.RegisterAllocator) []Code

Split this micro code using registers of arbirary width into one or more micro codes using registers of a fixed maximum width. Here, the environment maps registers in this instruction to their "limbs" (that is, registers after the split). For example, consider (where x,y,z are 16bit registers and b a 1 bit register):

> b, x := y + z + 1

Then, splitting to a maximum register width of 8bits yields the following:

> b,x1,x0 := (256*y1+y0) + (256*z1+z0) + 1

This is then factored as such:

> b,x1,x0 := 256*(y1+z1) + (y0+z0+1)

Thus, y0+z0+1 define all of the bits for x0 and some of the bits for x1.

func (*Assign) String 

func (p *Assign) String(fn register.Map) string

func (*Assign) Validate 

func (p *Assign) Validate(fieldWidth uint, fn register.Map) error

Validate checks whether or not this instruction is correctly balanced.

type Cast 

type Cast struct {
	CastWidth uint
	// Target registers for cast
	Targets []io.RegisterId
	// Source register for cast
	Source io.RegisterId
}

Cast provides a construct for (safely) casting a register into a narrower set of registers. For example, assignment a 16bit register into an 8bit register. The cast is safe in the sense that it will cause an exception if the value assigned does not fit.

func (*Cast) Clone 

func (p *Cast) Clone() Code

Clone this micro code.

func (*Cast) MicroExecute 

func (p *Cast) MicroExecute(state io.State) (uint, uint)

MicroExecute implementation for Code interface.

func (*Cast) RegistersRead 

func (p *Cast) RegistersRead() []io.RegisterId

RegistersRead implementation for Instruction interface.

func (*Cast) RegistersWritten 

func (p *Cast) RegistersWritten() []io.RegisterId

RegistersWritten implementation for Instruction interface.

func (*Cast) Split 

func (p *Cast) Split(mapping register.LimbsMap, _ agnostic.RegisterAllocator) []Code

Split implementation for Code interface.

func (*Cast) String 

func (p *Cast) String(fn register.Map) string

func (*Cast) Validate 

func (p *Cast) Validate(fieldWidth uint, fn register.Map) error

Validate implementation for Instruction interface.

type Code 

type Code interface {
	// Clone this instruction
	Clone() Code
	// Execute a given micro-code, using a given local state.  This may update
	// the register values, and returns either the number of micro-codes to
	// "skip over" when executing the enclosing instruction or, if skip==0, a
	// destination program counter (which can signal return of enclosing
	// function).
	MicroExecute(state io.State) (skip uint, pc uint)
	// Registers returns the set of registers read this micro instruction.
	RegistersRead() []io.RegisterId
	// Registers returns the set of registers written by this micro instruction.
	RegistersWritten() []io.RegisterId
	// Produce a suitable string representation of this instruction.  This is
	// primarily used for debugging.
	String(register.Map) string
	// Split this micro code using registers of arbirary width into one or more
	// micro codes using registers of a fixed maximum width.
	Split(mapping register.LimbsMap, env agnostic.RegisterAllocator) []Code
	// Validate that this instruction is well-formed.  For example, that it is
	// balanced, that there are no conflicting writes, that all temporaries have
	// been allocated, etc.  The maximum bit capacity of the underlying field is
	// needed for this calculation, so as to allow an instruction to check it
	// does not overflow the underlying field.
	Validate(fieldWidth uint, fn register.Map) error
}

Code provides an abstract notion of an atomic "machine operation", where a single instruction is comprised of multiple such microcodes. To ensure efficiency, we want to pack as many microcodes into each instruction as we can. However, there are restrictions here meaning we cannot pack arbitrarily many microcodes into a single instruction. For example, we cannot pack two microcodes together which have conflicting writes (i.e. both write to the same register).

type Division 

type Division struct {
	// Target registers (grouped into limbs)
	Quotient, Remainder, Witness register.Vector
	// Dividend and right comparisons
	Dividend, Divisor VecExpr
}

Division operator divides either a register (or constant) by another register (or constant) producing a quotient and a remainder.

func (*Division) Clone 

func (p *Division) Clone() Code

Clone this micro code.

func (*Division) MicroExecute 

func (p *Division) MicroExecute(state io.State) (uint, uint)

MicroExecute implementation for Code interface.

func (*Division) RegistersRead 

func (p *Division) RegistersRead() []io.RegisterId

RegistersRead implementation for Code interface.

func (*Division) RegistersWritten 

func (p *Division) RegistersWritten() []io.RegisterId

RegistersWritten implementation for Code interface.

func (*Division) Split 

func (p *Division) Split(mapping register.LimbsMap, _ agnostic.RegisterAllocator) []Code

Split implementation for Code interface.

func (*Division) String 

func (p *Division) String(fn register.Map) string

func (*Division) Validate 

func (p *Division) Validate(fieldWidth uint, fn register.Map) error

Validate implementation for Code interface.

type Expr 

type Expr struct {
	util.Union[io.RegisterId, big.Int]
}

Expr represents an expression at the micro level, which is either a register access or a constant.

func NewConstant 

func NewConstant(c big.Int) Expr

NewConstant constructs an expression representing a constant.

func NewConstant64 

func NewConstant64(c uint64) Expr

NewConstant64 constructs an expression representing a constant.

func NewRegister 

func NewRegister(r io.RegisterId) Expr

NewRegister constructs an expression representing a register access

func (Expr) Bitwidth 

func (e Expr) Bitwidth(fn register.Map) uint

Bitwidth returns the minimum number of bits required to store any evaluation of this expression.

func (Expr) Clone 

func (e Expr) Clone() Expr

Clone this expression

func (Expr) Eval 

func (e Expr) Eval(state io.State) *big.Int

Eval evaluates a set of zero or more expressions producing a set of zero or more values.

func (Expr) String 

func (e Expr) String(fn register.Map) string

func (Expr) ToVec 

func (e Expr) ToVec() VecExpr

ToVec converts this expression into a vectorizable expression.

type Fail 

type Fail struct {
	// contains filtered or unexported fields
}

Fail signals a return from the enclosing function.

func (*Fail) Clone 

func (p *Fail) Clone() Code

Clone this micro code.

func (*Fail) MicroExecute 

func (p *Fail) MicroExecute(state io.State) (uint, uint)

MicroExecute a given micro-code, using a given local state. This may update the register values, and returns either the number of micro-codes to "skip over" when executing the enclosing instruction or, if skip==0, a destination program counter (which can signal return of enclosing function).

func (*Fail) RegistersRead 

func (p *Fail) RegistersRead() []io.RegisterId

RegistersRead returns the set of registers read by this instruction.

func (*Fail) RegistersWritten 

func (p *Fail) RegistersWritten() []io.RegisterId

RegistersWritten returns the set of registers written by this instruction.

func (*Fail) Split 

func (p *Fail) Split(mapping register.LimbsMap, env agnostic.RegisterAllocator) []Code

Split this micro code using registers of arbirary width into one or more micro codes using registers of a fixed maximum width.

func (*Fail) String 

func (p *Fail) String(fn register.Map) string

func (*Fail) Validate 

func (p *Fail) Validate(fieldWidth uint, fn register.Map) error

Validate checks whether or not this instruction is correctly balanced.

type InOut 

type InOut struct {
	// contains filtered or unexported fields
}

InOut captures input / output instructions for reading / writing to a bus.

func NewIoRead 

func NewIoRead(bus io.Bus) *InOut

NewIoRead constructs an instruction responsible for reading data to a given bus.

func NewIoWrite 

func NewIoWrite(bus io.Bus) *InOut

NewIoWrite constructs an instruction responsible for writing data to a given bus.

func (*InOut) Bus 

func (p *InOut) Bus() io.Bus

Bus returns information about the bus. Observe that prior to Link being called, this will return an unlinked bus.

func (*InOut) Clone 

func (p *InOut) Clone() Code

Clone this micro code.

func (*InOut) MicroExecute 

func (p *InOut) MicroExecute(state io.State) (uint, uint)

MicroExecute a given micro-code, using a given local state. This may update the register values, and returns either the number of micro-codes to "skip over" when executing the enclosing instruction or, if skip==0, a destination program counter (which can signal return of enclosing function).

func (*InOut) RegistersRead 

func (p *InOut) RegistersRead() []io.RegisterId

RegistersRead returns the set of registers read by this instruction.

func (*InOut) RegistersWritten 

func (p *InOut) RegistersWritten() []io.RegisterId

RegistersWritten returns the set of registers written by this instruction.

func (*InOut) Split 

func (p *InOut) Split(mapping register.LimbsMap, _ agnostic.RegisterAllocator) []Code

Split this micro code using registers of arbirary width into one or more micro codes using registers of a fixed maximum width.

func (*InOut) String 

func (p *InOut) String(fn register.Map) string

func (*InOut) Validate 

func (p *InOut) Validate(fieldWidth uint, fn register.Map) error

Validate checks whether or not this instruction is correctly balanced.

type Instruction 

type Instruction struct {
	Codes []Code
}

Instruction represents the composition of one or more micro instructions which are to be executed "in parallel". This roughly following the ideas of vector machines and vectorisation. In order to ensure parallel execution is safe, there are restrictions on how microcodes can be combined. For example, two microcodes writing to the same register are said to be "conflicting" and, hence, this is not permitted. Likewise, it is not possible to branch into the middle of a microinstruction.

func NewInstruction 

func NewInstruction(codes ...Code) Instruction

NewInstruction constructs a new instruction from a given set of micro-codes.

func (Instruction) BranchTable 

func (p Instruction) BranchTable() dfa.Result[dfa.Branch]

BranchTable constructs a per-micro-code slice giving, for each constituent micro-code, the condition under which control reaches it. The condition is expressed in terms of the values of registers as observed _on entry to the vector instruction_: it is a disjunction (over execution paths) of conjunctions (the SkipIf comparisons taken — or not taken — along the path). The entry micro-code therefore always has condition TRUE, while later micro-codes accumulate the SkipIf guards of the path that reaches them.

The table is built by a forward data-flow analysis over the micro-codes. Unconditional terminators (Fail, Ret, Jmp) propagate nothing; an unconditional Skip propagates the incoming condition to its target; SkipIf splits into the "skip taken" condition (joined into the skip target) and the "skip not taken" condition (joined into the following micro-code). Where multiple paths converge on the same micro-code, their conditions are or-joined.

The pre-computed write map is needed because the conditions reference registers which may have been freshly written earlier in the same vector; each BranchGroupId records whether forwarding is in effect for that reference, which is determined by consulting the write state at the SkipIf's offset.

func (Instruction) Execute 

func (p Instruction) Execute(state io.State) uint

Execute this instruction with the given local and global state. The next program counter position is returned, or io.RETURN if the enclosing function has terminated (i.e. because a return instruction was encountered).

func (Instruction) JumpTargets 

func (p Instruction) JumpTargets() []uint

JumpTargets returns the set of all jump targets used within this instruction. This is relatively easy to determine simply by looking for jmp codes.

func (Instruction) LastJump 

func (p Instruction) LastJump(n uint) (uint, bool)

LastJump returns the index of the right-most jmp instruction (or false if none exists). This is relatively easy to determine simply by looking for jmp codes.

func (Instruction) Registers 

func (p Instruction) Registers() []io.RegisterId

Registers returns the set of registers read/written by this instruction.

func (Instruction) RegistersRead 

func (p Instruction) RegistersRead() []io.RegisterId

RegistersRead returns the set of registers read by this instruction.

func (Instruction) RegistersWritten 

func (p Instruction) RegistersWritten() []io.RegisterId

RegistersWritten returns the set of registers written by this instruction.

func (Instruction) SplitRegisters 

func (p Instruction) SplitRegisters(mapping register.LimbsMap, env agnostic.RegisterAllocator) Instruction

SplitRegisters implementation for the SplittableInstruction interface. A key challenge for this method is the correct handling of skip instructions. Specifically, the targets for a skip change as the number of instructions increase.

func (Instruction) String 

func (p Instruction) String(fn register.Map) string

func (Instruction) Terminal 

func (p Instruction) Terminal() bool

Terminal checks whether or not this instruction can result in a return from the enclosing function. That is, whether or not this instruction contains a "ret" micro-code.

func (Instruction) Validate 

func (p Instruction) Validate(fieldWidth uint, fn register.Map) error

Validate that this micro-instruction is well-formed. For example, each micro-instruction contained within must be well-formed, and the overall requirements for a vector instruction must be met, etc.

func (Instruction) Writes 

func (p Instruction) Writes() dfa.Result[dfa.Writes]

Writes constructs the write map for this micro instruction.

type Jmp 

type Jmp struct {
	Target uint
}

Jmp provides an unconditional branching instruction to a given instructon.

func (*Jmp) Clone 

func (p *Jmp) Clone() Code

Clone this micro code.

func (*Jmp) MicroExecute 

func (p *Jmp) MicroExecute(state io.State) (uint, uint)

MicroExecute a given micro-code, using a given local state. This may update the register values, and returns either the number of micro-codes to "skip over" when executing the enclosing instruction or, if skip==0, a destination program counter (which can signal return of enclosing function).

func (*Jmp) RegistersRead 

func (p *Jmp) RegistersRead() []io.RegisterId

RegistersRead returns the set of registers read by this instruction.

func (*Jmp) RegistersWritten 

func (p *Jmp) RegistersWritten() []io.RegisterId

RegistersWritten returns the set of registers written by this instruction.

func (*Jmp) Split 

func (p *Jmp) Split(register.LimbsMap, agnostic.RegisterAllocator) []Code

Split this micro code using registers of arbirary width into one or more micro codes using registers of a fixed maximum width.

func (*Jmp) String 

func (p *Jmp) String(fn register.Map) string

func (*Jmp) Validate 

func (p *Jmp) Validate(fieldWidth uint, fn register.Map) error

Validate checks whether or not this instruction is correctly balanced.

type Polynomial 

type Polynomial = agnostic.StaticPolynomial

Polynomial provides a useful alias which captures the fact that all polynomials in assembly are static. That is, we never consider the possibility that registers can be "shifted".

func LimbPolynomial 

func LimbPolynomial(limbs []register.Id, env register.LimbsMap) Polynomial

LimbPolynomial constructs a polynomial from the given limbs which represents the value of the original register. For example, suppose x is a u16 register which splits into two u8 limbs x'0 and x'1. Then, the constructed "limb polynomial" is simply x'0 + 256*x'1 (recall that x'0 is the last significant limb).

func SplitMonomial 

func SplitMonomial(p agnostic.StaticMonomial, env register.LimbsMap) Polynomial

SplitMonomial splits a given monomial (e.g. 2*x*y) according to a given register-to-limb mapping. For example, suppose x is u16 and maps to x'0 and x'1 (both u8), whilst y maps to itself. Then, the resulting polynomial is:

2*(x'0 + 256*x'1)*y --> (2*x'0*y) + (512*x'1*y)

Of course, things get more involved when more than one register is being split, but the basic idea above applies.

func SplitPolynomial 

func SplitPolynomial(p Polynomial, env register.LimbsMap) Polynomial

SplitPolynomial splits the registers in a given polynomial into their limbs, producing an equivalent (but not necessarily identical) polynomial. For example, suppose that X and Y split into limbs X'1, X'0 and Y'1, Y'0. Then the polynomial 2*X + Y splits into 512*X'1 + 2*X'0 + 256*Y'1 + Y'0.

type Ret 

type Ret struct {
	// contains filtered or unexported fields
}

Ret signals a return from the enclosing function.

func (*Ret) Clone 

func (p *Ret) Clone() Code

Clone this micro code.

func (*Ret) MicroExecute 

func (p *Ret) MicroExecute(state io.State) (uint, uint)

MicroExecute a given micro-code, using a given local state. This may update the register values, and returns either the number of micro-codes to "skip over" when executing the enclosing instruction or, if skip==0, a destination program counter (which can signal return of enclosing function).

func (*Ret) RegistersRead 

func (p *Ret) RegistersRead() []io.RegisterId

RegistersRead returns the set of registers read by this instruction.

func (*Ret) RegistersWritten 

func (p *Ret) RegistersWritten() []io.RegisterId

RegistersWritten returns the set of registers written by this instruction.

func (*Ret) Split 

func (p *Ret) Split(register.LimbsMap, agnostic.RegisterAllocator) []Code

Split this micro code using registers of arbirary width into one or more micro codes using registers of a fixed maximum width.

func (*Ret) String 

func (p *Ret) String(fn register.Map) string

func (*Ret) Validate 

func (p *Ret) Validate(fieldWidth uint, fn register.Map) error

Validate checks whether or not this instruction is correctly balanced.

type Skip 

type Skip struct {
	// Skip
	Skip uint
}

Skip microcode performs an unconditional skip over a given number of codes.

func (*Skip) Clone 

func (p *Skip) Clone() Code

Clone this micro code.

func (*Skip) MicroExecute 

func (p *Skip) MicroExecute(state io.State) (uint, uint)

MicroExecute a given micro-code, using a given local state. This may update the register values, and returns either the number of micro-codes to "skip over" when executing the enclosing instruction or, if skip==0, a destination program counter (which can signal return of enclosing function).

func (*Skip) RegistersRead 

func (p *Skip) RegistersRead() []io.RegisterId

RegistersRead returns the set of registers read by this instruction.

func (*Skip) RegistersWritten 

func (p *Skip) RegistersWritten() []io.RegisterId

RegistersWritten returns the set of registers written by this instruction.

func (*Skip) Split 

func (p *Skip) Split(mapping register.LimbsMap, _ agnostic.RegisterAllocator) []Code

Split this micro code using registers of arbirary width into one or more micro codes using registers of a fixed maximum width.

func (*Skip) String 

func (p *Skip) String(fn register.Map) string

func (*Skip) Validate 

func (p *Skip) Validate(fieldWidth uint, fn register.Map) error

Validate checks whether or not this instruction is correctly balanced.

type SkipIf 

type SkipIf struct {
	// Left and right comparisons
	Left register.Vector
	//
	Right VecExpr
	// Skip
	Skip uint
}

SkipIf microcode performs a conditional skip over a given number of codes. The condition is either that two registers are equal, or that they are not equal. This has two variants: register-register; and, register-constant. The latter is indiciated when the right register is marked as UNUSED.

func (*SkipIf) Clone 

func (p *SkipIf) Clone() Code

Clone this micro code.

func (*SkipIf) MicroExecute 

func (p *SkipIf) MicroExecute(state io.State) (uint, uint)

MicroExecute a given micro-code, using a given local state. This may update the register values, and returns either the number of micro-codes to "skip over" when executing the enclosing instruction or, if skip==0, a destination program counter (which can signal return of enclosing function).

func (*SkipIf) RegistersRead 

func (p *SkipIf) RegistersRead() []io.RegisterId

RegistersRead returns the set of registers read by this instruction.

func (*SkipIf) RegistersWritten 

func (p *SkipIf) RegistersWritten() []io.RegisterId

RegistersWritten returns the set of registers written by this instruction.

func (*SkipIf) Split 

func (p *SkipIf) Split(mapping register.LimbsMap, _ agnostic.RegisterAllocator) []Code

Split this micro code using registers of arbirary width into one or more micro codes using registers of a fixed maximum width.

func (*SkipIf) String 

func (p *SkipIf) String(fn register.Map) string

func (*SkipIf) Validate 

func (p *SkipIf) Validate(fieldWidth uint, fn register.Map) error

Validate checks whether or not this instruction is correctly balanced.

type VecExpr 

type VecExpr struct {
	util.Union[register.Vector, big.Int]
}

VecExpr represents an vectorizeable expression at the micro level, which is either a vector of register accesses or a constant.

func ConstVecExpr 

func ConstVecExpr(c big.Int) VecExpr

ConstVecExpr constructs an vectorizable expression from a constant.

func NewVecExpr 

func NewVecExpr(regs register.Vector) VecExpr

NewVecExpr constructs an vectorizable expression from a register vector.

func (VecExpr) Bitwidth 

func (e VecExpr) Bitwidth(fn register.Map) uint

Bitwidth returns the minimum number of bits required to store any evaluation of this expression.

func (VecExpr) Eval 

func (e VecExpr) Eval(state io.State) *big.Int

Eval evaluates a set of zero or more expressions producing a set of zero or more values.

func (VecExpr) Split 

func (e VecExpr) Split(mapping register.LimbsMap) VecExpr

Split this vectorizable expression according to a given limbs mapping.

func (VecExpr) String 

func (e VecExpr) String(fn register.Map) string

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Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
 Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.

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