nvml

const (
	// NO_UNVERSIONED_FUNC_DEFS as defined in go-nvml/<predefine>:24
	NO_UNVERSIONED_FUNC_DEFS = 1
	// API_VERSION as defined in nvml/nvml.h
	API_VERSION = 13
	// API_VERSION_STR as defined in nvml/nvml.h
	API_VERSION_STR = "13"
	// VALUE_NOT_AVAILABLE as defined in nvml/nvml.h
	VALUE_NOT_AVAILABLE = -1
	// DEVICE_PCI_BUS_ID_BUFFER_SIZE as defined in nvml/nvml.h
	DEVICE_PCI_BUS_ID_BUFFER_SIZE = 32
	// DEVICE_PCI_BUS_ID_BUFFER_V2_SIZE as defined in nvml/nvml.h
	DEVICE_PCI_BUS_ID_BUFFER_V2_SIZE = 16
	// DEVICE_PCI_BUS_ID_LEGACY_FMT as defined in nvml/nvml.h
	DEVICE_PCI_BUS_ID_LEGACY_FMT = "%04X:%02X:%02X.0"
	// DEVICE_PCI_BUS_ID_FMT as defined in nvml/nvml.h
	DEVICE_PCI_BUS_ID_FMT = "%08X:%02X:%02X.0"
	// NVLINK_MAX_LINKS as defined in nvml/nvml.h
	NVLINK_MAX_LINKS = 18
	// TOPOLOGY_CPU as defined in nvml/nvml.h
	TOPOLOGY_CPU = 0
	// MAX_PHYSICAL_BRIDGE as defined in nvml/nvml.h
	MAX_PHYSICAL_BRIDGE = 128
	// MAX_THERMAL_SENSORS_PER_GPU as defined in nvml/nvml.h
	MAX_THERMAL_SENSORS_PER_GPU = 3
	// DEVICE_UUID_ASCII_LEN as defined in nvml/nvml.h
	DEVICE_UUID_ASCII_LEN = 41
	// DEVICE_UUID_BINARY_LEN as defined in nvml/nvml.h
	DEVICE_UUID_BINARY_LEN = 16
	// FlagDefault as defined in nvml/nvml.h
	FlagDefault = 0
	// FlagForce as defined in nvml/nvml.h
	FlagForce = 1
	// SINGLE_BIT_ECC as defined in nvml/nvml.h
	SINGLE_BIT_ECC = 0
	// DOUBLE_BIT_ECC as defined in nvml/nvml.h
	DOUBLE_BIT_ECC = 0
	// MAX_GPU_PERF_PSTATES as defined in nvml/nvml.h
	MAX_GPU_PERF_PSTATES = 16
	// PERF_MODES_BUFFER_SIZE as defined in nvml/nvml.h
	PERF_MODES_BUFFER_SIZE = 2048
	// POWER_MIZER_MODE_ADAPTIVE as defined in nvml/nvml.h
	POWER_MIZER_MODE_ADAPTIVE = 0
	// POWER_MIZER_MODE_PREFER_MAXIMUM_PERFORMANCE as defined in nvml/nvml.h
	POWER_MIZER_MODE_PREFER_MAXIMUM_PERFORMANCE = 1
	// POWER_MIZER_MODE_AUTO as defined in nvml/nvml.h
	POWER_MIZER_MODE_AUTO = 2
	// POWER_MIZER_MODE_PREFER_CONSISTENT_PERFORMANCE as defined in nvml/nvml.h
	POWER_MIZER_MODE_PREFER_CONSISTENT_PERFORMANCE = 3
	// GSP_FIRMWARE_VERSION_BUF_SIZE as defined in nvml/nvml.h
	GSP_FIRMWARE_VERSION_BUF_SIZE = 64
	// DEVICE_ARCH_KEPLER as defined in nvml/nvml.h
	DEVICE_ARCH_KEPLER = 2
	// DEVICE_ARCH_MAXWELL as defined in nvml/nvml.h
	DEVICE_ARCH_MAXWELL = 3
	// DEVICE_ARCH_PASCAL as defined in nvml/nvml.h
	DEVICE_ARCH_PASCAL = 4
	// DEVICE_ARCH_VOLTA as defined in nvml/nvml.h
	DEVICE_ARCH_VOLTA = 5
	// DEVICE_ARCH_TURING as defined in nvml/nvml.h
	DEVICE_ARCH_TURING = 6
	// DEVICE_ARCH_AMPERE as defined in nvml/nvml.h
	DEVICE_ARCH_AMPERE = 7
	// DEVICE_ARCH_ADA as defined in nvml/nvml.h
	DEVICE_ARCH_ADA = 8
	// DEVICE_ARCH_HOPPER as defined in nvml/nvml.h
	DEVICE_ARCH_HOPPER = 9
	// DEVICE_ARCH_BLACKWELL as defined in nvml/nvml.h
	DEVICE_ARCH_BLACKWELL = 10
	// DEVICE_ARCH_UNKNOWN as defined in nvml/nvml.h
	DEVICE_ARCH_UNKNOWN = 4294967295
	// BUS_TYPE_UNKNOWN as defined in nvml/nvml.h
	BUS_TYPE_UNKNOWN = 0
	// BUS_TYPE_PCI as defined in nvml/nvml.h
	BUS_TYPE_PCI = 1
	// BUS_TYPE_PCIE as defined in nvml/nvml.h
	BUS_TYPE_PCIE = 2
	// BUS_TYPE_FPCI as defined in nvml/nvml.h
	BUS_TYPE_FPCI = 3
	// BUS_TYPE_AGP as defined in nvml/nvml.h
	BUS_TYPE_AGP = 4
	// FAN_POLICY_TEMPERATURE_CONTINOUS_SW as defined in nvml/nvml.h
	FAN_POLICY_TEMPERATURE_CONTINOUS_SW = 0
	// FAN_POLICY_MANUAL as defined in nvml/nvml.h
	FAN_POLICY_MANUAL = 1
	// POWER_SOURCE_AC as defined in nvml/nvml.h
	POWER_SOURCE_AC = 0
	// POWER_SOURCE_BATTERY as defined in nvml/nvml.h
	POWER_SOURCE_BATTERY = 1
	// POWER_SOURCE_UNDERSIZED as defined in nvml/nvml.h
	POWER_SOURCE_UNDERSIZED = 2
	// PCIE_LINK_MAX_SPEED_INVALID as defined in nvml/nvml.h
	PCIE_LINK_MAX_SPEED_INVALID = 0
	// PCIE_LINK_MAX_SPEED_2500MBPS as defined in nvml/nvml.h
	PCIE_LINK_MAX_SPEED_2500MBPS = 1
	// PCIE_LINK_MAX_SPEED_5000MBPS as defined in nvml/nvml.h
	PCIE_LINK_MAX_SPEED_5000MBPS = 2
	// PCIE_LINK_MAX_SPEED_8000MBPS as defined in nvml/nvml.h
	PCIE_LINK_MAX_SPEED_8000MBPS = 3
	// PCIE_LINK_MAX_SPEED_16000MBPS as defined in nvml/nvml.h
	PCIE_LINK_MAX_SPEED_16000MBPS = 4
	// PCIE_LINK_MAX_SPEED_32000MBPS as defined in nvml/nvml.h
	PCIE_LINK_MAX_SPEED_32000MBPS = 5
	// PCIE_LINK_MAX_SPEED_64000MBPS as defined in nvml/nvml.h
	PCIE_LINK_MAX_SPEED_64000MBPS = 6
	// ADAPTIVE_CLOCKING_INFO_STATUS_DISABLED as defined in nvml/nvml.h
	ADAPTIVE_CLOCKING_INFO_STATUS_DISABLED = 0
	// ADAPTIVE_CLOCKING_INFO_STATUS_ENABLED as defined in nvml/nvml.h
	ADAPTIVE_CLOCKING_INFO_STATUS_ENABLED = 1
	// MAX_GPU_UTILIZATIONS as defined in nvml/nvml.h
	MAX_GPU_UTILIZATIONS = 8
	// PCIE_ATOMICS_CAP_FETCHADD32 as defined in nvml/nvml.h
	PCIE_ATOMICS_CAP_FETCHADD32 = 1
	// PCIE_ATOMICS_CAP_FETCHADD64 as defined in nvml/nvml.h
	PCIE_ATOMICS_CAP_FETCHADD64 = 2
	// PCIE_ATOMICS_CAP_SWAP32 as defined in nvml/nvml.h
	PCIE_ATOMICS_CAP_SWAP32 = 4
	// PCIE_ATOMICS_CAP_SWAP64 as defined in nvml/nvml.h
	PCIE_ATOMICS_CAP_SWAP64 = 8
	// PCIE_ATOMICS_CAP_CAS32 as defined in nvml/nvml.h
	PCIE_ATOMICS_CAP_CAS32 = 16
	// PCIE_ATOMICS_CAP_CAS64 as defined in nvml/nvml.h
	PCIE_ATOMICS_CAP_CAS64 = 32
	// PCIE_ATOMICS_CAP_CAS128 as defined in nvml/nvml.h
	PCIE_ATOMICS_CAP_CAS128 = 64
	// PCIE_ATOMICS_OPS_MAX as defined in nvml/nvml.h
	PCIE_ATOMICS_OPS_MAX = 7
	// POWER_SCOPE_GPU as defined in nvml/nvml.h
	POWER_SCOPE_GPU = 0
	// POWER_SCOPE_MODULE as defined in nvml/nvml.h
	POWER_SCOPE_MODULE = 1
	// POWER_SCOPE_MEMORY as defined in nvml/nvml.h
	POWER_SCOPE_MEMORY = 2
	// GRID_LICENSE_EXPIRY_NOT_AVAILABLE as defined in nvml/nvml.h
	GRID_LICENSE_EXPIRY_NOT_AVAILABLE = 0
	// GRID_LICENSE_EXPIRY_INVALID as defined in nvml/nvml.h
	GRID_LICENSE_EXPIRY_INVALID = 1
	// GRID_LICENSE_EXPIRY_VALID as defined in nvml/nvml.h
	GRID_LICENSE_EXPIRY_VALID = 2
	// GRID_LICENSE_EXPIRY_NOT_APPLICABLE as defined in nvml/nvml.h
	GRID_LICENSE_EXPIRY_NOT_APPLICABLE = 3
	// GRID_LICENSE_EXPIRY_PERMANENT as defined in nvml/nvml.h
	GRID_LICENSE_EXPIRY_PERMANENT = 4
	// GRID_LICENSE_BUFFER_SIZE as defined in nvml/nvml.h
	GRID_LICENSE_BUFFER_SIZE = 128
	// VGPU_NAME_BUFFER_SIZE as defined in nvml/nvml.h
	VGPU_NAME_BUFFER_SIZE = 64
	// GRID_LICENSE_FEATURE_MAX_COUNT as defined in nvml/nvml.h
	GRID_LICENSE_FEATURE_MAX_COUNT = 3
	// INVALID_VGPU_PLACEMENT_ID as defined in nvml/nvml.h
	INVALID_VGPU_PLACEMENT_ID = 65535
	// VGPU_PGPU_HETEROGENEOUS_MODE as defined in nvml/nvml.h
	VGPU_PGPU_HETEROGENEOUS_MODE = 0
	// VGPU_PGPU_HOMOGENEOUS_MODE as defined in nvml/nvml.h
	VGPU_PGPU_HOMOGENEOUS_MODE = 1
	// VGPU_SCHEDULER_POLICY_UNKNOWN as defined in nvml/nvml.h
	VGPU_SCHEDULER_POLICY_UNKNOWN = 0
	// VGPU_SCHEDULER_POLICY_BEST_EFFORT as defined in nvml/nvml.h
	VGPU_SCHEDULER_POLICY_BEST_EFFORT = 1
	// VGPU_SCHEDULER_POLICY_EQUAL_SHARE as defined in nvml/nvml.h
	VGPU_SCHEDULER_POLICY_EQUAL_SHARE = 2
	// VGPU_SCHEDULER_POLICY_FIXED_SHARE as defined in nvml/nvml.h
	VGPU_SCHEDULER_POLICY_FIXED_SHARE = 3
	// SUPPORTED_VGPU_SCHEDULER_POLICY_COUNT as defined in nvml/nvml.h
	SUPPORTED_VGPU_SCHEDULER_POLICY_COUNT = 3
	// SCHEDULER_SW_MAX_LOG_ENTRIES as defined in nvml/nvml.h
	SCHEDULER_SW_MAX_LOG_ENTRIES = 200
	// VGPU_SCHEDULER_ARR_DEFAULT as defined in nvml/nvml.h
	VGPU_SCHEDULER_ARR_DEFAULT = 0
	// VGPU_SCHEDULER_ARR_DISABLE as defined in nvml/nvml.h
	VGPU_SCHEDULER_ARR_DISABLE = 1
	// VGPU_SCHEDULER_ARR_ENABLE as defined in nvml/nvml.h
	VGPU_SCHEDULER_ARR_ENABLE = 2
	// VGPU_SCHEDULER_ENGINE_TYPE_GRAPHICS as defined in nvml/nvml.h
	VGPU_SCHEDULER_ENGINE_TYPE_GRAPHICS = 1
	// GRID_LICENSE_STATE_UNKNOWN as defined in nvml/nvml.h
	GRID_LICENSE_STATE_UNKNOWN = 0
	// GRID_LICENSE_STATE_UNINITIALIZED as defined in nvml/nvml.h
	GRID_LICENSE_STATE_UNINITIALIZED = 1
	// GRID_LICENSE_STATE_UNLICENSED_UNRESTRICTED as defined in nvml/nvml.h
	GRID_LICENSE_STATE_UNLICENSED_UNRESTRICTED = 2
	// GRID_LICENSE_STATE_UNLICENSED_RESTRICTED as defined in nvml/nvml.h
	GRID_LICENSE_STATE_UNLICENSED_RESTRICTED = 3
	// GRID_LICENSE_STATE_UNLICENSED as defined in nvml/nvml.h
	GRID_LICENSE_STATE_UNLICENSED = 4
	// GRID_LICENSE_STATE_LICENSED as defined in nvml/nvml.h
	GRID_LICENSE_STATE_LICENSED = 5
	// FI_DEV_ECC_CURRENT as defined in nvml/nvml.h
	FI_DEV_ECC_CURRENT = 1
	// FI_DEV_ECC_PENDING as defined in nvml/nvml.h
	FI_DEV_ECC_PENDING = 2
	// FI_DEV_ECC_SBE_VOL_TOTAL as defined in nvml/nvml.h
	FI_DEV_ECC_SBE_VOL_TOTAL = 3
	// FI_DEV_ECC_DBE_VOL_TOTAL as defined in nvml/nvml.h
	FI_DEV_ECC_DBE_VOL_TOTAL = 4
	// FI_DEV_ECC_SBE_AGG_TOTAL as defined in nvml/nvml.h
	FI_DEV_ECC_SBE_AGG_TOTAL = 5
	// FI_DEV_ECC_DBE_AGG_TOTAL as defined in nvml/nvml.h
	FI_DEV_ECC_DBE_AGG_TOTAL = 6
	// FI_DEV_ECC_SBE_VOL_L1 as defined in nvml/nvml.h
	FI_DEV_ECC_SBE_VOL_L1 = 7
	// FI_DEV_ECC_DBE_VOL_L1 as defined in nvml/nvml.h
	FI_DEV_ECC_DBE_VOL_L1 = 8
	// FI_DEV_ECC_SBE_VOL_L2 as defined in nvml/nvml.h
	FI_DEV_ECC_SBE_VOL_L2 = 9
	// FI_DEV_ECC_DBE_VOL_L2 as defined in nvml/nvml.h
	FI_DEV_ECC_DBE_VOL_L2 = 10
	// FI_DEV_ECC_SBE_VOL_DEV as defined in nvml/nvml.h
	FI_DEV_ECC_SBE_VOL_DEV = 11
	// FI_DEV_ECC_DBE_VOL_DEV as defined in nvml/nvml.h
	FI_DEV_ECC_DBE_VOL_DEV = 12
	// FI_DEV_ECC_SBE_VOL_REG as defined in nvml/nvml.h
	FI_DEV_ECC_SBE_VOL_REG = 13
	// FI_DEV_ECC_DBE_VOL_REG as defined in nvml/nvml.h
	FI_DEV_ECC_DBE_VOL_REG = 14
	// FI_DEV_ECC_SBE_VOL_TEX as defined in nvml/nvml.h
	FI_DEV_ECC_SBE_VOL_TEX = 15
	// FI_DEV_ECC_DBE_VOL_TEX as defined in nvml/nvml.h
	FI_DEV_ECC_DBE_VOL_TEX = 16
	// FI_DEV_ECC_DBE_VOL_CBU as defined in nvml/nvml.h
	FI_DEV_ECC_DBE_VOL_CBU = 17
	// FI_DEV_ECC_SBE_AGG_L1 as defined in nvml/nvml.h
	FI_DEV_ECC_SBE_AGG_L1 = 18
	// FI_DEV_ECC_DBE_AGG_L1 as defined in nvml/nvml.h
	FI_DEV_ECC_DBE_AGG_L1 = 19
	// FI_DEV_ECC_SBE_AGG_L2 as defined in nvml/nvml.h
	FI_DEV_ECC_SBE_AGG_L2 = 20
	// FI_DEV_ECC_DBE_AGG_L2 as defined in nvml/nvml.h
	FI_DEV_ECC_DBE_AGG_L2 = 21
	// FI_DEV_ECC_SBE_AGG_DEV as defined in nvml/nvml.h
	FI_DEV_ECC_SBE_AGG_DEV = 22
	// FI_DEV_ECC_DBE_AGG_DEV as defined in nvml/nvml.h
	FI_DEV_ECC_DBE_AGG_DEV = 23
	// FI_DEV_ECC_SBE_AGG_REG as defined in nvml/nvml.h
	FI_DEV_ECC_SBE_AGG_REG = 24
	// FI_DEV_ECC_DBE_AGG_REG as defined in nvml/nvml.h
	FI_DEV_ECC_DBE_AGG_REG = 25
	// FI_DEV_ECC_SBE_AGG_TEX as defined in nvml/nvml.h
	FI_DEV_ECC_SBE_AGG_TEX = 26
	// FI_DEV_ECC_DBE_AGG_TEX as defined in nvml/nvml.h
	FI_DEV_ECC_DBE_AGG_TEX = 27
	// FI_DEV_ECC_DBE_AGG_CBU as defined in nvml/nvml.h
	FI_DEV_ECC_DBE_AGG_CBU = 28
	// FI_DEV_RETIRED_SBE as defined in nvml/nvml.h
	FI_DEV_RETIRED_SBE = 29
	// FI_DEV_RETIRED_DBE as defined in nvml/nvml.h
	FI_DEV_RETIRED_DBE = 30
	// FI_DEV_RETIRED_PENDING as defined in nvml/nvml.h
	FI_DEV_RETIRED_PENDING = 31
	// FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L0 as defined in nvml/nvml.h
	FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L0 = 32
	// FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L1 as defined in nvml/nvml.h
	FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L1 = 33
	// FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L2 as defined in nvml/nvml.h
	FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L2 = 34
	// FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L3 as defined in nvml/nvml.h
	FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L3 = 35
	// FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L4 as defined in nvml/nvml.h
	FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L4 = 36
	// FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L5 as defined in nvml/nvml.h
	FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L5 = 37
	// FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_TOTAL as defined in nvml/nvml.h
	FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_TOTAL = 38
	// FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L0 as defined in nvml/nvml.h
	FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L0 = 39
	// FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L1 as defined in nvml/nvml.h
	FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L1 = 40
	// FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L2 as defined in nvml/nvml.h
	FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L2 = 41
	// FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L3 as defined in nvml/nvml.h
	FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L3 = 42
	// FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L4 as defined in nvml/nvml.h
	FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L4 = 43
	// FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L5 as defined in nvml/nvml.h
	FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L5 = 44
	// FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_TOTAL as defined in nvml/nvml.h
	FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_TOTAL = 45
	// FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L0 as defined in nvml/nvml.h
	FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L0 = 46
	// FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L1 as defined in nvml/nvml.h
	FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L1 = 47
	// FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L2 as defined in nvml/nvml.h
	FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L2 = 48
	// FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L3 as defined in nvml/nvml.h
	FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L3 = 49
	// FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L4 as defined in nvml/nvml.h
	FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L4 = 50
	// FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L5 as defined in nvml/nvml.h
	FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L5 = 51
	// FI_DEV_NVLINK_REPLAY_ERROR_COUNT_TOTAL as defined in nvml/nvml.h
	FI_DEV_NVLINK_REPLAY_ERROR_COUNT_TOTAL = 52
	// FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L0 as defined in nvml/nvml.h
	FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L0 = 53
	// FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L1 as defined in nvml/nvml.h
	FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L1 = 54
	// FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L2 as defined in nvml/nvml.h
	FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L2 = 55
	// FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L3 as defined in nvml/nvml.h
	FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L3 = 56
	// FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L4 as defined in nvml/nvml.h
	FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L4 = 57
	// FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L5 as defined in nvml/nvml.h
	FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L5 = 58
	// FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_TOTAL as defined in nvml/nvml.h
	FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_TOTAL = 59
	// FI_DEV_NVLINK_BANDWIDTH_C0_L0 as defined in nvml/nvml.h
	FI_DEV_NVLINK_BANDWIDTH_C0_L0 = 60
	// FI_DEV_NVLINK_BANDWIDTH_C0_L1 as defined in nvml/nvml.h
	FI_DEV_NVLINK_BANDWIDTH_C0_L1 = 61
	// FI_DEV_NVLINK_BANDWIDTH_C0_L2 as defined in nvml/nvml.h
	FI_DEV_NVLINK_BANDWIDTH_C0_L2 = 62
	// FI_DEV_NVLINK_BANDWIDTH_C0_L3 as defined in nvml/nvml.h
	FI_DEV_NVLINK_BANDWIDTH_C0_L3 = 63
	// FI_DEV_NVLINK_BANDWIDTH_C0_L4 as defined in nvml/nvml.h
	FI_DEV_NVLINK_BANDWIDTH_C0_L4 = 64
	// FI_DEV_NVLINK_BANDWIDTH_C0_L5 as defined in nvml/nvml.h
	FI_DEV_NVLINK_BANDWIDTH_C0_L5 = 65
	// FI_DEV_NVLINK_BANDWIDTH_C0_TOTAL as defined in nvml/nvml.h
	FI_DEV_NVLINK_BANDWIDTH_C0_TOTAL = 66
	// FI_DEV_NVLINK_BANDWIDTH_C1_L0 as defined in nvml/nvml.h
	FI_DEV_NVLINK_BANDWIDTH_C1_L0 = 67
	// FI_DEV_NVLINK_BANDWIDTH_C1_L1 as defined in nvml/nvml.h
	FI_DEV_NVLINK_BANDWIDTH_C1_L1 = 68
	// FI_DEV_NVLINK_BANDWIDTH_C1_L2 as defined in nvml/nvml.h
	FI_DEV_NVLINK_BANDWIDTH_C1_L2 = 69
	// FI_DEV_NVLINK_BANDWIDTH_C1_L3 as defined in nvml/nvml.h
	FI_DEV_NVLINK_BANDWIDTH_C1_L3 = 70
	// FI_DEV_NVLINK_BANDWIDTH_C1_L4 as defined in nvml/nvml.h
	FI_DEV_NVLINK_BANDWIDTH_C1_L4 = 71
	// FI_DEV_NVLINK_BANDWIDTH_C1_L5 as defined in nvml/nvml.h
	FI_DEV_NVLINK_BANDWIDTH_C1_L5 = 72
	// FI_DEV_NVLINK_BANDWIDTH_C1_TOTAL as defined in nvml/nvml.h
	FI_DEV_NVLINK_BANDWIDTH_C1_TOTAL = 73
	// FI_DEV_PERF_POLICY_POWER as defined in nvml/nvml.h
	FI_DEV_PERF_POLICY_POWER = 74
	// FI_DEV_PERF_POLICY_THERMAL as defined in nvml/nvml.h
	FI_DEV_PERF_POLICY_THERMAL = 75
	// FI_DEV_PERF_POLICY_SYNC_BOOST as defined in nvml/nvml.h
	FI_DEV_PERF_POLICY_SYNC_BOOST = 76
	// FI_DEV_PERF_POLICY_BOARD_LIMIT as defined in nvml/nvml.h
	FI_DEV_PERF_POLICY_BOARD_LIMIT = 77
	// FI_DEV_PERF_POLICY_LOW_UTILIZATION as defined in nvml/nvml.h
	FI_DEV_PERF_POLICY_LOW_UTILIZATION = 78
	// FI_DEV_PERF_POLICY_RELIABILITY as defined in nvml/nvml.h
	FI_DEV_PERF_POLICY_RELIABILITY = 79
	// FI_DEV_PERF_POLICY_TOTAL_APP_CLOCKS as defined in nvml/nvml.h
	FI_DEV_PERF_POLICY_TOTAL_APP_CLOCKS = 80
	// FI_DEV_PERF_POLICY_TOTAL_BASE_CLOCKS as defined in nvml/nvml.h
	FI_DEV_PERF_POLICY_TOTAL_BASE_CLOCKS = 81
	// FI_DEV_MEMORY_TEMP as defined in nvml/nvml.h
	FI_DEV_MEMORY_TEMP = 82
	// FI_DEV_TOTAL_ENERGY_CONSUMPTION as defined in nvml/nvml.h
	FI_DEV_TOTAL_ENERGY_CONSUMPTION = 83
	// FI_DEV_NVLINK_SPEED_MBPS_L0 as defined in nvml/nvml.h
	FI_DEV_NVLINK_SPEED_MBPS_L0 = 84
	// FI_DEV_NVLINK_SPEED_MBPS_L1 as defined in nvml/nvml.h
	FI_DEV_NVLINK_SPEED_MBPS_L1 = 85
	// FI_DEV_NVLINK_SPEED_MBPS_L2 as defined in nvml/nvml.h
	FI_DEV_NVLINK_SPEED_MBPS_L2 = 86
	// FI_DEV_NVLINK_SPEED_MBPS_L3 as defined in nvml/nvml.h
	FI_DEV_NVLINK_SPEED_MBPS_L3 = 87
	// FI_DEV_NVLINK_SPEED_MBPS_L4 as defined in nvml/nvml.h
	FI_DEV_NVLINK_SPEED_MBPS_L4 = 88
	// FI_DEV_NVLINK_SPEED_MBPS_L5 as defined in nvml/nvml.h
	FI_DEV_NVLINK_SPEED_MBPS_L5 = 89
	// FI_DEV_NVLINK_SPEED_MBPS_COMMON as defined in nvml/nvml.h
	FI_DEV_NVLINK_SPEED_MBPS_COMMON = 90
	// FI_DEV_NVLINK_LINK_COUNT as defined in nvml/nvml.h
	FI_DEV_NVLINK_LINK_COUNT = 91
	// FI_DEV_RETIRED_PENDING_SBE as defined in nvml/nvml.h
	FI_DEV_RETIRED_PENDING_SBE = 92
	// FI_DEV_RETIRED_PENDING_DBE as defined in nvml/nvml.h
	FI_DEV_RETIRED_PENDING_DBE = 93
	// FI_DEV_PCIE_REPLAY_COUNTER as defined in nvml/nvml.h
	FI_DEV_PCIE_REPLAY_COUNTER = 94
	// FI_DEV_PCIE_REPLAY_ROLLOVER_COUNTER as defined in nvml/nvml.h
	FI_DEV_PCIE_REPLAY_ROLLOVER_COUNTER = 95
	// FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L6 as defined in nvml/nvml.h
	FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L6 = 96
	// FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L7 as defined in nvml/nvml.h
	FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L7 = 97
	// FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L8 as defined in nvml/nvml.h
	FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L8 = 98
	// FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L9 as defined in nvml/nvml.h
	FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L9 = 99
	// FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L10 as defined in nvml/nvml.h
	FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L10 = 100
	// FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L11 as defined in nvml/nvml.h
	FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L11 = 101
	// FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L6 as defined in nvml/nvml.h
	FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L6 = 102
	// FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L7 as defined in nvml/nvml.h
	FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L7 = 103
	// FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L8 as defined in nvml/nvml.h
	FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L8 = 104
	// FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L9 as defined in nvml/nvml.h
	FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L9 = 105
	// FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L10 as defined in nvml/nvml.h
	FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L10 = 106
	// FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L11 as defined in nvml/nvml.h
	FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L11 = 107
	// FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L6 as defined in nvml/nvml.h
	FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L6 = 108
	// FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L7 as defined in nvml/nvml.h
	FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L7 = 109
	// FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L8 as defined in nvml/nvml.h
	FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L8 = 110
	// FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L9 as defined in nvml/nvml.h
	FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L9 = 111
	// FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L10 as defined in nvml/nvml.h
	FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L10 = 112
	// FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L11 as defined in nvml/nvml.h
	FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L11 = 113
	// FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L6 as defined in nvml/nvml.h
	FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L6 = 114
	// FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L7 as defined in nvml/nvml.h
	FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L7 = 115
	// FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L8 as defined in nvml/nvml.h
	FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L8 = 116
	// FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L9 as defined in nvml/nvml.h
	FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L9 = 117
	// FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L10 as defined in nvml/nvml.h
	FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L10 = 118
	// FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L11 as defined in nvml/nvml.h
	FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L11 = 119
	// FI_DEV_NVLINK_BANDWIDTH_C0_L6 as defined in nvml/nvml.h
	FI_DEV_NVLINK_BANDWIDTH_C0_L6 = 120
	// FI_DEV_NVLINK_BANDWIDTH_C0_L7 as defined in nvml/nvml.h
	FI_DEV_NVLINK_BANDWIDTH_C0_L7 = 121
	// FI_DEV_NVLINK_BANDWIDTH_C0_L8 as defined in nvml/nvml.h
	FI_DEV_NVLINK_BANDWIDTH_C0_L8 = 122
	// FI_DEV_NVLINK_BANDWIDTH_C0_L9 as defined in nvml/nvml.h
	FI_DEV_NVLINK_BANDWIDTH_C0_L9 = 123
	// FI_DEV_NVLINK_BANDWIDTH_C0_L10 as defined in nvml/nvml.h
	FI_DEV_NVLINK_BANDWIDTH_C0_L10 = 124
	// FI_DEV_NVLINK_BANDWIDTH_C0_L11 as defined in nvml/nvml.h
	FI_DEV_NVLINK_BANDWIDTH_C0_L11 = 125
	// FI_DEV_NVLINK_BANDWIDTH_C1_L6 as defined in nvml/nvml.h
	FI_DEV_NVLINK_BANDWIDTH_C1_L6 = 126
	// FI_DEV_NVLINK_BANDWIDTH_C1_L7 as defined in nvml/nvml.h
	FI_DEV_NVLINK_BANDWIDTH_C1_L7 = 127
	// FI_DEV_NVLINK_BANDWIDTH_C1_L8 as defined in nvml/nvml.h
	FI_DEV_NVLINK_BANDWIDTH_C1_L8 = 128
	// FI_DEV_NVLINK_BANDWIDTH_C1_L9 as defined in nvml/nvml.h
	FI_DEV_NVLINK_BANDWIDTH_C1_L9 = 129
	// FI_DEV_NVLINK_BANDWIDTH_C1_L10 as defined in nvml/nvml.h
	FI_DEV_NVLINK_BANDWIDTH_C1_L10 = 130
	// FI_DEV_NVLINK_BANDWIDTH_C1_L11 as defined in nvml/nvml.h
	FI_DEV_NVLINK_BANDWIDTH_C1_L11 = 131
	// FI_DEV_NVLINK_SPEED_MBPS_L6 as defined in nvml/nvml.h
	FI_DEV_NVLINK_SPEED_MBPS_L6 = 132
	// FI_DEV_NVLINK_SPEED_MBPS_L7 as defined in nvml/nvml.h
	FI_DEV_NVLINK_SPEED_MBPS_L7 = 133
	// FI_DEV_NVLINK_SPEED_MBPS_L8 as defined in nvml/nvml.h
	FI_DEV_NVLINK_SPEED_MBPS_L8 = 134
	// FI_DEV_NVLINK_SPEED_MBPS_L9 as defined in nvml/nvml.h
	FI_DEV_NVLINK_SPEED_MBPS_L9 = 135
	// FI_DEV_NVLINK_SPEED_MBPS_L10 as defined in nvml/nvml.h
	FI_DEV_NVLINK_SPEED_MBPS_L10 = 136
	// FI_DEV_NVLINK_SPEED_MBPS_L11 as defined in nvml/nvml.h
	FI_DEV_NVLINK_SPEED_MBPS_L11 = 137
	// FI_DEV_NVLINK_THROUGHPUT_DATA_TX as defined in nvml/nvml.h
	FI_DEV_NVLINK_THROUGHPUT_DATA_TX = 138
	// FI_DEV_NVLINK_THROUGHPUT_DATA_RX as defined in nvml/nvml.h
	FI_DEV_NVLINK_THROUGHPUT_DATA_RX = 139
	// FI_DEV_NVLINK_THROUGHPUT_RAW_TX as defined in nvml/nvml.h
	FI_DEV_NVLINK_THROUGHPUT_RAW_TX = 140
	// FI_DEV_NVLINK_THROUGHPUT_RAW_RX as defined in nvml/nvml.h
	FI_DEV_NVLINK_THROUGHPUT_RAW_RX = 141
	// FI_DEV_REMAPPED_COR as defined in nvml/nvml.h
	FI_DEV_REMAPPED_COR = 142
	// FI_DEV_REMAPPED_UNC as defined in nvml/nvml.h
	FI_DEV_REMAPPED_UNC = 143
	// FI_DEV_REMAPPED_PENDING as defined in nvml/nvml.h
	FI_DEV_REMAPPED_PENDING = 144
	// FI_DEV_REMAPPED_FAILURE as defined in nvml/nvml.h
	FI_DEV_REMAPPED_FAILURE = 145
	// FI_DEV_NVLINK_REMOTE_NVLINK_ID as defined in nvml/nvml.h
	FI_DEV_NVLINK_REMOTE_NVLINK_ID = 146
	// FI_DEV_NVSWITCH_CONNECTED_LINK_COUNT as defined in nvml/nvml.h
	FI_DEV_NVSWITCH_CONNECTED_LINK_COUNT = 147
	// FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L0 as defined in nvml/nvml.h
	FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L0 = 148
	// FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L1 as defined in nvml/nvml.h
	FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L1 = 149
	// FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L2 as defined in nvml/nvml.h
	FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L2 = 150
	// FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L3 as defined in nvml/nvml.h
	FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L3 = 151
	// FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L4 as defined in nvml/nvml.h
	FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L4 = 152
	// FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L5 as defined in nvml/nvml.h
	FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L5 = 153
	// FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L6 as defined in nvml/nvml.h
	FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L6 = 154
	// FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L7 as defined in nvml/nvml.h
	FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L7 = 155
	// FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L8 as defined in nvml/nvml.h
	FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L8 = 156
	// FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L9 as defined in nvml/nvml.h
	FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L9 = 157
	// FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L10 as defined in nvml/nvml.h
	FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L10 = 158
	// FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L11 as defined in nvml/nvml.h
	FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L11 = 159
	// FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_TOTAL as defined in nvml/nvml.h
	FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_TOTAL = 160
	// FI_DEV_NVLINK_ERROR_DL_REPLAY as defined in nvml/nvml.h
	FI_DEV_NVLINK_ERROR_DL_REPLAY = 161
	// FI_DEV_NVLINK_ERROR_DL_RECOVERY as defined in nvml/nvml.h
	FI_DEV_NVLINK_ERROR_DL_RECOVERY = 162
	// FI_DEV_NVLINK_ERROR_DL_CRC as defined in nvml/nvml.h
	FI_DEV_NVLINK_ERROR_DL_CRC = 163
	// FI_DEV_NVLINK_GET_SPEED as defined in nvml/nvml.h
	FI_DEV_NVLINK_GET_SPEED = 164
	// FI_DEV_NVLINK_GET_STATE as defined in nvml/nvml.h
	FI_DEV_NVLINK_GET_STATE = 165
	// FI_DEV_NVLINK_GET_VERSION as defined in nvml/nvml.h
	FI_DEV_NVLINK_GET_VERSION = 166
	// FI_DEV_NVLINK_GET_POWER_STATE as defined in nvml/nvml.h
	FI_DEV_NVLINK_GET_POWER_STATE = 167
	// FI_DEV_NVLINK_GET_POWER_THRESHOLD as defined in nvml/nvml.h
	FI_DEV_NVLINK_GET_POWER_THRESHOLD = 168
	// FI_DEV_PCIE_L0_TO_RECOVERY_COUNTER as defined in nvml/nvml.h
	FI_DEV_PCIE_L0_TO_RECOVERY_COUNTER = 169
	// FI_DEV_C2C_LINK_COUNT as defined in nvml/nvml.h
	FI_DEV_C2C_LINK_COUNT = 170
	// FI_DEV_C2C_LINK_GET_STATUS as defined in nvml/nvml.h
	FI_DEV_C2C_LINK_GET_STATUS = 171
	// FI_DEV_C2C_LINK_GET_MAX_BW as defined in nvml/nvml.h
	FI_DEV_C2C_LINK_GET_MAX_BW = 172
	// FI_DEV_PCIE_COUNT_CORRECTABLE_ERRORS as defined in nvml/nvml.h
	FI_DEV_PCIE_COUNT_CORRECTABLE_ERRORS = 173
	// FI_DEV_PCIE_COUNT_NAKS_RECEIVED as defined in nvml/nvml.h
	FI_DEV_PCIE_COUNT_NAKS_RECEIVED = 174
	// FI_DEV_PCIE_COUNT_RECEIVER_ERROR as defined in nvml/nvml.h
	FI_DEV_PCIE_COUNT_RECEIVER_ERROR = 175
	// FI_DEV_PCIE_COUNT_BAD_TLP as defined in nvml/nvml.h
	FI_DEV_PCIE_COUNT_BAD_TLP = 176
	// FI_DEV_PCIE_COUNT_NAKS_SENT as defined in nvml/nvml.h
	FI_DEV_PCIE_COUNT_NAKS_SENT = 177
	// FI_DEV_PCIE_COUNT_BAD_DLLP as defined in nvml/nvml.h
	FI_DEV_PCIE_COUNT_BAD_DLLP = 178
	// FI_DEV_PCIE_COUNT_NON_FATAL_ERROR as defined in nvml/nvml.h
	FI_DEV_PCIE_COUNT_NON_FATAL_ERROR = 179
	// FI_DEV_PCIE_COUNT_FATAL_ERROR as defined in nvml/nvml.h
	FI_DEV_PCIE_COUNT_FATAL_ERROR = 180
	// FI_DEV_PCIE_COUNT_UNSUPPORTED_REQ as defined in nvml/nvml.h
	FI_DEV_PCIE_COUNT_UNSUPPORTED_REQ = 181
	// FI_DEV_PCIE_COUNT_LCRC_ERROR as defined in nvml/nvml.h
	FI_DEV_PCIE_COUNT_LCRC_ERROR = 182
	// FI_DEV_PCIE_COUNT_LANE_ERROR as defined in nvml/nvml.h
	FI_DEV_PCIE_COUNT_LANE_ERROR = 183
	// FI_DEV_IS_RESETLESS_MIG_SUPPORTED as defined in nvml/nvml.h
	FI_DEV_IS_RESETLESS_MIG_SUPPORTED = 184
	// FI_DEV_POWER_AVERAGE as defined in nvml/nvml.h
	FI_DEV_POWER_AVERAGE = 185
	// FI_DEV_POWER_INSTANT as defined in nvml/nvml.h
	FI_DEV_POWER_INSTANT = 186
	// FI_DEV_POWER_MIN_LIMIT as defined in nvml/nvml.h
	FI_DEV_POWER_MIN_LIMIT = 187
	// FI_DEV_POWER_MAX_LIMIT as defined in nvml/nvml.h
	FI_DEV_POWER_MAX_LIMIT = 188
	// FI_DEV_POWER_DEFAULT_LIMIT as defined in nvml/nvml.h
	FI_DEV_POWER_DEFAULT_LIMIT = 189
	// FI_DEV_POWER_CURRENT_LIMIT as defined in nvml/nvml.h
	FI_DEV_POWER_CURRENT_LIMIT = 190
	// FI_DEV_ENERGY as defined in nvml/nvml.h
	FI_DEV_ENERGY = 191
	// FI_DEV_POWER_REQUESTED_LIMIT as defined in nvml/nvml.h
	FI_DEV_POWER_REQUESTED_LIMIT = 192
	// FI_DEV_TEMPERATURE_SHUTDOWN_TLIMIT as defined in nvml/nvml.h
	FI_DEV_TEMPERATURE_SHUTDOWN_TLIMIT = 193
	// FI_DEV_TEMPERATURE_SLOWDOWN_TLIMIT as defined in nvml/nvml.h
	FI_DEV_TEMPERATURE_SLOWDOWN_TLIMIT = 194
	// FI_DEV_TEMPERATURE_MEM_MAX_TLIMIT as defined in nvml/nvml.h
	FI_DEV_TEMPERATURE_MEM_MAX_TLIMIT = 195
	// FI_DEV_TEMPERATURE_GPU_MAX_TLIMIT as defined in nvml/nvml.h
	FI_DEV_TEMPERATURE_GPU_MAX_TLIMIT = 196
	// FI_DEV_PCIE_COUNT_TX_BYTES as defined in nvml/nvml.h
	FI_DEV_PCIE_COUNT_TX_BYTES = 197
	// FI_DEV_PCIE_COUNT_RX_BYTES as defined in nvml/nvml.h
	FI_DEV_PCIE_COUNT_RX_BYTES = 198
	// FI_DEV_IS_MIG_MODE_INDEPENDENT_MIG_QUERY_CAPABLE as defined in nvml/nvml.h
	FI_DEV_IS_MIG_MODE_INDEPENDENT_MIG_QUERY_CAPABLE = 199
	// FI_DEV_NVLINK_GET_POWER_THRESHOLD_MAX as defined in nvml/nvml.h
	FI_DEV_NVLINK_GET_POWER_THRESHOLD_MAX = 200
	// FI_DEV_NVLINK_COUNT_XMIT_PACKETS as defined in nvml/nvml.h
	FI_DEV_NVLINK_COUNT_XMIT_PACKETS = 201
	// FI_DEV_NVLINK_COUNT_XMIT_BYTES as defined in nvml/nvml.h
	FI_DEV_NVLINK_COUNT_XMIT_BYTES = 202
	// FI_DEV_NVLINK_COUNT_RCV_PACKETS as defined in nvml/nvml.h
	FI_DEV_NVLINK_COUNT_RCV_PACKETS = 203
	// FI_DEV_NVLINK_COUNT_RCV_BYTES as defined in nvml/nvml.h
	FI_DEV_NVLINK_COUNT_RCV_BYTES = 204
	// FI_DEV_NVLINK_COUNT_VL15_DROPPED as defined in nvml/nvml.h
	FI_DEV_NVLINK_COUNT_VL15_DROPPED = 205
	// FI_DEV_NVLINK_COUNT_MALFORMED_PACKET_ERRORS as defined in nvml/nvml.h
	FI_DEV_NVLINK_COUNT_MALFORMED_PACKET_ERRORS = 206
	// FI_DEV_NVLINK_COUNT_BUFFER_OVERRUN_ERRORS as defined in nvml/nvml.h
	FI_DEV_NVLINK_COUNT_BUFFER_OVERRUN_ERRORS = 207
	// FI_DEV_NVLINK_COUNT_RCV_ERRORS as defined in nvml/nvml.h
	FI_DEV_NVLINK_COUNT_RCV_ERRORS = 208
	// FI_DEV_NVLINK_COUNT_RCV_REMOTE_ERRORS as defined in nvml/nvml.h
	FI_DEV_NVLINK_COUNT_RCV_REMOTE_ERRORS = 209
	// FI_DEV_NVLINK_COUNT_RCV_GENERAL_ERRORS as defined in nvml/nvml.h
	FI_DEV_NVLINK_COUNT_RCV_GENERAL_ERRORS = 210
	// FI_DEV_NVLINK_COUNT_LOCAL_LINK_INTEGRITY_ERRORS as defined in nvml/nvml.h
	FI_DEV_NVLINK_COUNT_LOCAL_LINK_INTEGRITY_ERRORS = 211
	// FI_DEV_NVLINK_COUNT_XMIT_DISCARDS as defined in nvml/nvml.h
	FI_DEV_NVLINK_COUNT_XMIT_DISCARDS = 212
	// FI_DEV_NVLINK_COUNT_LINK_RECOVERY_SUCCESSFUL_EVENTS as defined in nvml/nvml.h
	FI_DEV_NVLINK_COUNT_LINK_RECOVERY_SUCCESSFUL_EVENTS = 213
	// FI_DEV_NVLINK_COUNT_LINK_RECOVERY_FAILED_EVENTS as defined in nvml/nvml.h
	FI_DEV_NVLINK_COUNT_LINK_RECOVERY_FAILED_EVENTS = 214
	// FI_DEV_NVLINK_COUNT_LINK_RECOVERY_EVENTS as defined in nvml/nvml.h
	FI_DEV_NVLINK_COUNT_LINK_RECOVERY_EVENTS = 215
	// FI_DEV_NVLINK_COUNT_RAW_BER_LANE0 as defined in nvml/nvml.h
	FI_DEV_NVLINK_COUNT_RAW_BER_LANE0 = 216
	// FI_DEV_NVLINK_COUNT_RAW_BER_LANE1 as defined in nvml/nvml.h
	FI_DEV_NVLINK_COUNT_RAW_BER_LANE1 = 217
	// FI_DEV_NVLINK_COUNT_RAW_BER as defined in nvml/nvml.h
	FI_DEV_NVLINK_COUNT_RAW_BER = 218
	// FI_DEV_NVLINK_COUNT_EFFECTIVE_ERRORS as defined in nvml/nvml.h
	FI_DEV_NVLINK_COUNT_EFFECTIVE_ERRORS = 219
	// FI_DEV_NVLINK_COUNT_EFFECTIVE_BER as defined in nvml/nvml.h
	FI_DEV_NVLINK_COUNT_EFFECTIVE_BER = 220
	// FI_DEV_NVLINK_COUNT_SYMBOL_ERRORS as defined in nvml/nvml.h
	FI_DEV_NVLINK_COUNT_SYMBOL_ERRORS = 221
	// FI_DEV_NVLINK_COUNT_SYMBOL_BER as defined in nvml/nvml.h
	FI_DEV_NVLINK_COUNT_SYMBOL_BER = 222
	// FI_DEV_NVLINK_GET_POWER_THRESHOLD_MIN as defined in nvml/nvml.h
	FI_DEV_NVLINK_GET_POWER_THRESHOLD_MIN = 223
	// FI_DEV_NVLINK_GET_POWER_THRESHOLD_UNITS as defined in nvml/nvml.h
	FI_DEV_NVLINK_GET_POWER_THRESHOLD_UNITS = 224
	// FI_DEV_NVLINK_GET_POWER_THRESHOLD_SUPPORTED as defined in nvml/nvml.h
	FI_DEV_NVLINK_GET_POWER_THRESHOLD_SUPPORTED = 225
	// FI_DEV_RESET_STATUS as defined in nvml/nvml.h
	FI_DEV_RESET_STATUS = 226
	// FI_DEV_DRAIN_AND_RESET_STATUS as defined in nvml/nvml.h
	FI_DEV_DRAIN_AND_RESET_STATUS = 227
	// FI_DEV_PCIE_OUTBOUND_ATOMICS_MASK as defined in nvml/nvml.h
	FI_DEV_PCIE_OUTBOUND_ATOMICS_MASK = 228
	// FI_DEV_PCIE_INBOUND_ATOMICS_MASK as defined in nvml/nvml.h
	FI_DEV_PCIE_INBOUND_ATOMICS_MASK = 229
	// FI_DEV_GET_GPU_RECOVERY_ACTION as defined in nvml/nvml.h
	FI_DEV_GET_GPU_RECOVERY_ACTION = 230
	// FI_DEV_C2C_LINK_ERROR_INTR as defined in nvml/nvml.h
	FI_DEV_C2C_LINK_ERROR_INTR = 231
	// FI_DEV_C2C_LINK_ERROR_REPLAY as defined in nvml/nvml.h
	FI_DEV_C2C_LINK_ERROR_REPLAY = 232
	// FI_DEV_C2C_LINK_ERROR_REPLAY_B2B as defined in nvml/nvml.h
	FI_DEV_C2C_LINK_ERROR_REPLAY_B2B = 233
	// FI_DEV_C2C_LINK_POWER_STATE as defined in nvml/nvml.h
	FI_DEV_C2C_LINK_POWER_STATE = 234
	// FI_DEV_NVLINK_COUNT_FEC_HISTORY_0 as defined in nvml/nvml.h
	FI_DEV_NVLINK_COUNT_FEC_HISTORY_0 = 235
	// FI_DEV_NVLINK_COUNT_FEC_HISTORY_1 as defined in nvml/nvml.h
	FI_DEV_NVLINK_COUNT_FEC_HISTORY_1 = 236
	// FI_DEV_NVLINK_COUNT_FEC_HISTORY_2 as defined in nvml/nvml.h
	FI_DEV_NVLINK_COUNT_FEC_HISTORY_2 = 237
	// FI_DEV_NVLINK_COUNT_FEC_HISTORY_3 as defined in nvml/nvml.h
	FI_DEV_NVLINK_COUNT_FEC_HISTORY_3 = 238
	// FI_DEV_NVLINK_COUNT_FEC_HISTORY_4 as defined in nvml/nvml.h
	FI_DEV_NVLINK_COUNT_FEC_HISTORY_4 = 239
	// FI_DEV_NVLINK_COUNT_FEC_HISTORY_5 as defined in nvml/nvml.h
	FI_DEV_NVLINK_COUNT_FEC_HISTORY_5 = 240
	// FI_DEV_NVLINK_COUNT_FEC_HISTORY_6 as defined in nvml/nvml.h
	FI_DEV_NVLINK_COUNT_FEC_HISTORY_6 = 241
	// FI_DEV_NVLINK_COUNT_FEC_HISTORY_7 as defined in nvml/nvml.h
	FI_DEV_NVLINK_COUNT_FEC_HISTORY_7 = 242
	// FI_DEV_NVLINK_COUNT_FEC_HISTORY_8 as defined in nvml/nvml.h
	FI_DEV_NVLINK_COUNT_FEC_HISTORY_8 = 243
	// FI_DEV_NVLINK_COUNT_FEC_HISTORY_9 as defined in nvml/nvml.h
	FI_DEV_NVLINK_COUNT_FEC_HISTORY_9 = 244
	// FI_DEV_NVLINK_COUNT_FEC_HISTORY_10 as defined in nvml/nvml.h
	FI_DEV_NVLINK_COUNT_FEC_HISTORY_10 = 245
	// FI_DEV_NVLINK_COUNT_FEC_HISTORY_11 as defined in nvml/nvml.h
	FI_DEV_NVLINK_COUNT_FEC_HISTORY_11 = 246
	// FI_DEV_NVLINK_COUNT_FEC_HISTORY_12 as defined in nvml/nvml.h
	FI_DEV_NVLINK_COUNT_FEC_HISTORY_12 = 247
	// FI_DEV_NVLINK_COUNT_FEC_HISTORY_13 as defined in nvml/nvml.h
	FI_DEV_NVLINK_COUNT_FEC_HISTORY_13 = 248
	// FI_DEV_NVLINK_COUNT_FEC_HISTORY_14 as defined in nvml/nvml.h
	FI_DEV_NVLINK_COUNT_FEC_HISTORY_14 = 249
	// FI_DEV_NVLINK_COUNT_FEC_HISTORY_15 as defined in nvml/nvml.h
	FI_DEV_NVLINK_COUNT_FEC_HISTORY_15 = 250
	// FI_DEV_CLOCKS_EVENT_REASON_SW_POWER_CAP as defined in nvml/nvml.h
	FI_DEV_CLOCKS_EVENT_REASON_SW_POWER_CAP = 74
	// FI_DEV_CLOCKS_EVENT_REASON_SYNC_BOOST as defined in nvml/nvml.h
	FI_DEV_CLOCKS_EVENT_REASON_SYNC_BOOST = 76
	// FI_DEV_CLOCKS_EVENT_REASON_SW_THERM_SLOWDOWN as defined in nvml/nvml.h
	FI_DEV_CLOCKS_EVENT_REASON_SW_THERM_SLOWDOWN = 251
	// FI_DEV_CLOCKS_EVENT_REASON_HW_THERM_SLOWDOWN as defined in nvml/nvml.h
	FI_DEV_CLOCKS_EVENT_REASON_HW_THERM_SLOWDOWN = 252
	// FI_DEV_CLOCKS_EVENT_REASON_HW_POWER_BRAKE_SLOWDOWN as defined in nvml/nvml.h
	FI_DEV_CLOCKS_EVENT_REASON_HW_POWER_BRAKE_SLOWDOWN = 253
	// FI_DEV_POWER_SYNC_BALANCING_FREQ as defined in nvml/nvml.h
	FI_DEV_POWER_SYNC_BALANCING_FREQ = 254
	// FI_DEV_POWER_SYNC_BALANCING_AF as defined in nvml/nvml.h
	FI_DEV_POWER_SYNC_BALANCING_AF = 255
	// FI_PWR_SMOOTHING_ENABLED as defined in nvml/nvml.h
	FI_PWR_SMOOTHING_ENABLED = 256
	// FI_PWR_SMOOTHING_PRIV_LVL as defined in nvml/nvml.h
	FI_PWR_SMOOTHING_PRIV_LVL = 257
	// FI_PWR_SMOOTHING_IMM_RAMP_DOWN_ENABLED as defined in nvml/nvml.h
	FI_PWR_SMOOTHING_IMM_RAMP_DOWN_ENABLED = 258
	// FI_PWR_SMOOTHING_APPLIED_TMP_CEIL as defined in nvml/nvml.h
	FI_PWR_SMOOTHING_APPLIED_TMP_CEIL = 259
	// FI_PWR_SMOOTHING_APPLIED_TMP_FLOOR as defined in nvml/nvml.h
	FI_PWR_SMOOTHING_APPLIED_TMP_FLOOR = 260
	// FI_PWR_SMOOTHING_MAX_PERCENT_TMP_FLOOR_SETTING as defined in nvml/nvml.h
	FI_PWR_SMOOTHING_MAX_PERCENT_TMP_FLOOR_SETTING = 261
	// FI_PWR_SMOOTHING_MIN_PERCENT_TMP_FLOOR_SETTING as defined in nvml/nvml.h
	FI_PWR_SMOOTHING_MIN_PERCENT_TMP_FLOOR_SETTING = 262
	// FI_PWR_SMOOTHING_HW_CIRCUITRY_PERCENT_LIFETIME_REMAINING as defined in nvml/nvml.h
	FI_PWR_SMOOTHING_HW_CIRCUITRY_PERCENT_LIFETIME_REMAINING = 263
	// FI_PWR_SMOOTHING_MAX_NUM_PRESET_PROFILES as defined in nvml/nvml.h
	FI_PWR_SMOOTHING_MAX_NUM_PRESET_PROFILES = 264
	// FI_PWR_SMOOTHING_PROFILE_PERCENT_TMP_FLOOR as defined in nvml/nvml.h
	FI_PWR_SMOOTHING_PROFILE_PERCENT_TMP_FLOOR = 265
	// FI_PWR_SMOOTHING_PROFILE_RAMP_UP_RATE as defined in nvml/nvml.h
	FI_PWR_SMOOTHING_PROFILE_RAMP_UP_RATE = 266
	// FI_PWR_SMOOTHING_PROFILE_RAMP_DOWN_RATE as defined in nvml/nvml.h
	FI_PWR_SMOOTHING_PROFILE_RAMP_DOWN_RATE = 267
	// FI_PWR_SMOOTHING_PROFILE_RAMP_DOWN_HYST_VAL as defined in nvml/nvml.h
	FI_PWR_SMOOTHING_PROFILE_RAMP_DOWN_HYST_VAL = 268
	// FI_PWR_SMOOTHING_ACTIVE_PRESET_PROFILE as defined in nvml/nvml.h
	FI_PWR_SMOOTHING_ACTIVE_PRESET_PROFILE = 269
	// FI_PWR_SMOOTHING_ADMIN_OVERRIDE_PERCENT_TMP_FLOOR as defined in nvml/nvml.h
	FI_PWR_SMOOTHING_ADMIN_OVERRIDE_PERCENT_TMP_FLOOR = 270
	// FI_PWR_SMOOTHING_ADMIN_OVERRIDE_RAMP_UP_RATE as defined in nvml/nvml.h
	FI_PWR_SMOOTHING_ADMIN_OVERRIDE_RAMP_UP_RATE = 271
	// FI_PWR_SMOOTHING_ADMIN_OVERRIDE_RAMP_DOWN_RATE as defined in nvml/nvml.h
	FI_PWR_SMOOTHING_ADMIN_OVERRIDE_RAMP_DOWN_RATE = 272
	// FI_PWR_SMOOTHING_ADMIN_OVERRIDE_RAMP_DOWN_HYST_VAL as defined in nvml/nvml.h
	FI_PWR_SMOOTHING_ADMIN_OVERRIDE_RAMP_DOWN_HYST_VAL = 273
	// FI_MAX as defined in nvml/nvml.h
	FI_MAX = 274
	// NVLINK_LOW_POWER_THRESHOLD_UNIT_100US as defined in nvml/nvml.h
	NVLINK_LOW_POWER_THRESHOLD_UNIT_100US = 0
	// NVLINK_LOW_POWER_THRESHOLD_UNIT_50US as defined in nvml/nvml.h
	NVLINK_LOW_POWER_THRESHOLD_UNIT_50US = 1
	// NVLINK_POWER_STATE_HIGH_SPEED as defined in nvml/nvml.h
	NVLINK_POWER_STATE_HIGH_SPEED = 0
	// NVLINK_POWER_STATE_LOW as defined in nvml/nvml.h
	NVLINK_POWER_STATE_LOW = 1
	// NVLINK_LOW_POWER_THRESHOLD_MIN as defined in nvml/nvml.h
	NVLINK_LOW_POWER_THRESHOLD_MIN = 1
	// NVLINK_LOW_POWER_THRESHOLD_MAX as defined in nvml/nvml.h
	NVLINK_LOW_POWER_THRESHOLD_MAX = 8191
	// NVLINK_LOW_POWER_THRESHOLD_RESET as defined in nvml/nvml.h
	NVLINK_LOW_POWER_THRESHOLD_RESET = 4294967295
	// NVLINK_LOW_POWER_THRESHOLD_DEFAULT as defined in nvml/nvml.h
	NVLINK_LOW_POWER_THRESHOLD_DEFAULT = 4294967295
	// C2C_POWER_STATE_FULL_POWER as defined in nvml/nvml.h
	C2C_POWER_STATE_FULL_POWER = 0
	// C2C_POWER_STATE_LOW_POWER as defined in nvml/nvml.h
	C2C_POWER_STATE_LOW_POWER = 1
	// EventTypeNone as defined in nvml/nvml.h
	EventTypeNone = 0
	// EventTypeSingleBitEccError as defined in nvml/nvml.h
	EventTypeSingleBitEccError = 1
	// EventTypeDoubleBitEccError as defined in nvml/nvml.h
	EventTypeDoubleBitEccError = 2
	// EventTypePState as defined in nvml/nvml.h
	EventTypePState = 4
	// EventTypeXidCriticalError as defined in nvml/nvml.h
	EventTypeXidCriticalError = 8
	// EventTypeClock as defined in nvml/nvml.h
	EventTypeClock = 16
	// EventTypePowerSourceChange as defined in nvml/nvml.h
	EventTypePowerSourceChange = 128
	// EventMigConfigChange as defined in nvml/nvml.h
	EventMigConfigChange = 256
	// EventTypeSingleBitEccErrorStorm as defined in nvml/nvml.h
	EventTypeSingleBitEccErrorStorm = 512
	// EventTypeDramRetirementEvent as defined in nvml/nvml.h
	EventTypeDramRetirementEvent = 1024
	// EventTypeDramRetirementFailure as defined in nvml/nvml.h
	EventTypeDramRetirementFailure = 2048
	// EventTypeNonFatalPoisonError as defined in nvml/nvml.h
	EventTypeNonFatalPoisonError = 4096
	// EventTypeFatalPoisonError as defined in nvml/nvml.h
	EventTypeFatalPoisonError = 8192
	// EventTypeGpuUnavailableError as defined in nvml/nvml.h
	EventTypeGpuUnavailableError = 16384
	// EventTypeGpuRecoveryAction as defined in nvml/nvml.h
	EventTypeGpuRecoveryAction = 32768
	// EventTypeAll as defined in nvml/nvml.h
	EventTypeAll = 65439
	// SystemEventTypeGpuDriverUnbind as defined in nvml/nvml.h
	SystemEventTypeGpuDriverUnbind = 1
	// SystemEventTypeGpuDriverBind as defined in nvml/nvml.h
	SystemEventTypeGpuDriverBind = 2
	// SystemEventTypeCount as defined in nvml/nvml.h
	SystemEventTypeCount = 2
	// ClocksEventReasonGpuIdle as defined in nvml/nvml.h
	ClocksEventReasonGpuIdle = 1
	// ClocksEventReasonApplicationsClocksSetting as defined in nvml/nvml.h
	ClocksEventReasonApplicationsClocksSetting = 2
	// ClocksThrottleReasonUserDefinedClocks as defined in nvml/nvml.h
	ClocksThrottleReasonUserDefinedClocks = 2
	// ClocksEventReasonSwPowerCap as defined in nvml/nvml.h
	ClocksEventReasonSwPowerCap = 4
	// ClocksThrottleReasonHwSlowdown as defined in nvml/nvml.h
	ClocksThrottleReasonHwSlowdown = 8
	// ClocksEventReasonSyncBoost as defined in nvml/nvml.h
	ClocksEventReasonSyncBoost = 16
	// ClocksEventReasonSwThermalSlowdown as defined in nvml/nvml.h
	ClocksEventReasonSwThermalSlowdown = 32
	// ClocksThrottleReasonHwThermalSlowdown as defined in nvml/nvml.h
	ClocksThrottleReasonHwThermalSlowdown = 64
	// ClocksThrottleReasonHwPowerBrakeSlowdown as defined in nvml/nvml.h
	ClocksThrottleReasonHwPowerBrakeSlowdown = 128
	// ClocksEventReasonDisplayClockSetting as defined in nvml/nvml.h
	ClocksEventReasonDisplayClockSetting = 256
	// ClocksEventReasonNone as defined in nvml/nvml.h
	ClocksEventReasonNone = 0
	// ClocksEventReasonAll as defined in nvml/nvml.h
	ClocksEventReasonAll = 511
	// ClocksThrottleReasonGpuIdle as defined in nvml/nvml.h
	ClocksThrottleReasonGpuIdle = 1
	// ClocksThrottleReasonApplicationsClocksSetting as defined in nvml/nvml.h
	ClocksThrottleReasonApplicationsClocksSetting = 2
	// ClocksThrottleReasonSyncBoost as defined in nvml/nvml.h
	ClocksThrottleReasonSyncBoost = 16
	// ClocksThrottleReasonSwPowerCap as defined in nvml/nvml.h
	ClocksThrottleReasonSwPowerCap = 4
	// ClocksThrottleReasonSwThermalSlowdown as defined in nvml/nvml.h
	ClocksThrottleReasonSwThermalSlowdown = 32
	// ClocksThrottleReasonDisplayClockSetting as defined in nvml/nvml.h
	ClocksThrottleReasonDisplayClockSetting = 256
	// ClocksThrottleReasonNone as defined in nvml/nvml.h
	ClocksThrottleReasonNone = 0
	// ClocksThrottleReasonAll as defined in nvml/nvml.h
	ClocksThrottleReasonAll = 511
	// NVFBC_SESSION_FLAG_DIFFMAP_ENABLED as defined in nvml/nvml.h
	NVFBC_SESSION_FLAG_DIFFMAP_ENABLED = 1
	// NVFBC_SESSION_FLAG_CLASSIFICATIONMAP_ENABLED as defined in nvml/nvml.h
	NVFBC_SESSION_FLAG_CLASSIFICATIONMAP_ENABLED = 2
	// NVFBC_SESSION_FLAG_CAPTURE_WITH_WAIT_NO_WAIT as defined in nvml/nvml.h
	NVFBC_SESSION_FLAG_CAPTURE_WITH_WAIT_NO_WAIT = 4
	// NVFBC_SESSION_FLAG_CAPTURE_WITH_WAIT_INFINITE as defined in nvml/nvml.h
	NVFBC_SESSION_FLAG_CAPTURE_WITH_WAIT_INFINITE = 8
	// NVFBC_SESSION_FLAG_CAPTURE_WITH_WAIT_TIMEOUT as defined in nvml/nvml.h
	NVFBC_SESSION_FLAG_CAPTURE_WITH_WAIT_TIMEOUT = 16
	// CC_SYSTEM_CPU_CAPS_NONE as defined in nvml/nvml.h
	CC_SYSTEM_CPU_CAPS_NONE = 0
	// CC_SYSTEM_CPU_CAPS_AMD_SEV as defined in nvml/nvml.h
	CC_SYSTEM_CPU_CAPS_AMD_SEV = 1
	// CC_SYSTEM_CPU_CAPS_INTEL_TDX as defined in nvml/nvml.h
	CC_SYSTEM_CPU_CAPS_INTEL_TDX = 2
	// CC_SYSTEM_CPU_CAPS_AMD_SEV_SNP as defined in nvml/nvml.h
	CC_SYSTEM_CPU_CAPS_AMD_SEV_SNP = 3
	// CC_SYSTEM_CPU_CAPS_AMD_SNP_VTOM as defined in nvml/nvml.h
	CC_SYSTEM_CPU_CAPS_AMD_SNP_VTOM = 4
	// CC_SYSTEM_GPUS_CC_NOT_CAPABLE as defined in nvml/nvml.h
	CC_SYSTEM_GPUS_CC_NOT_CAPABLE = 0
	// CC_SYSTEM_GPUS_CC_CAPABLE as defined in nvml/nvml.h
	CC_SYSTEM_GPUS_CC_CAPABLE = 1
	// CC_SYSTEM_DEVTOOLS_MODE_OFF as defined in nvml/nvml.h
	CC_SYSTEM_DEVTOOLS_MODE_OFF = 0
	// CC_SYSTEM_DEVTOOLS_MODE_ON as defined in nvml/nvml.h
	CC_SYSTEM_DEVTOOLS_MODE_ON = 1
	// CC_SYSTEM_ENVIRONMENT_UNAVAILABLE as defined in nvml/nvml.h
	CC_SYSTEM_ENVIRONMENT_UNAVAILABLE = 0
	// CC_SYSTEM_ENVIRONMENT_SIM as defined in nvml/nvml.h
	CC_SYSTEM_ENVIRONMENT_SIM = 1
	// CC_SYSTEM_ENVIRONMENT_PROD as defined in nvml/nvml.h
	CC_SYSTEM_ENVIRONMENT_PROD = 2
	// CC_SYSTEM_FEATURE_DISABLED as defined in nvml/nvml.h
	CC_SYSTEM_FEATURE_DISABLED = 0
	// CC_SYSTEM_FEATURE_ENABLED as defined in nvml/nvml.h
	CC_SYSTEM_FEATURE_ENABLED = 1
	// CC_SYSTEM_MULTIGPU_NONE as defined in nvml/nvml.h
	CC_SYSTEM_MULTIGPU_NONE = 0
	// CC_SYSTEM_MULTIGPU_PROTECTED_PCIE as defined in nvml/nvml.h
	CC_SYSTEM_MULTIGPU_PROTECTED_PCIE = 1
	// CC_SYSTEM_MULTIGPU_NVLE as defined in nvml/nvml.h
	CC_SYSTEM_MULTIGPU_NVLE = 2
	// CC_ACCEPTING_CLIENT_REQUESTS_FALSE as defined in nvml/nvml.h
	CC_ACCEPTING_CLIENT_REQUESTS_FALSE = 0
	// CC_ACCEPTING_CLIENT_REQUESTS_TRUE as defined in nvml/nvml.h
	CC_ACCEPTING_CLIENT_REQUESTS_TRUE = 1
	// GPU_CERT_CHAIN_SIZE as defined in nvml/nvml.h
	GPU_CERT_CHAIN_SIZE = 4096
	// GPU_ATTESTATION_CERT_CHAIN_SIZE as defined in nvml/nvml.h
	GPU_ATTESTATION_CERT_CHAIN_SIZE = 5120
	// CC_GPU_CEC_NONCE_SIZE as defined in nvml/nvml.h
	CC_GPU_CEC_NONCE_SIZE = 32
	// CC_GPU_ATTESTATION_REPORT_SIZE as defined in nvml/nvml.h
	CC_GPU_ATTESTATION_REPORT_SIZE = 8192
	// CC_GPU_CEC_ATTESTATION_REPORT_SIZE as defined in nvml/nvml.h
	CC_GPU_CEC_ATTESTATION_REPORT_SIZE = 4096
	// CC_CEC_ATTESTATION_REPORT_NOT_PRESENT as defined in nvml/nvml.h
	CC_CEC_ATTESTATION_REPORT_NOT_PRESENT = 0
	// CC_CEC_ATTESTATION_REPORT_PRESENT as defined in nvml/nvml.h
	CC_CEC_ATTESTATION_REPORT_PRESENT = 1
	// CC_KEY_ROTATION_THRESHOLD_ATTACKER_ADVANTAGE_MIN as defined in nvml/nvml.h
	CC_KEY_ROTATION_THRESHOLD_ATTACKER_ADVANTAGE_MIN = 50
	// CC_KEY_ROTATION_THRESHOLD_ATTACKER_ADVANTAGE_MAX as defined in nvml/nvml.h
	CC_KEY_ROTATION_THRESHOLD_ATTACKER_ADVANTAGE_MAX = 65
	// GPU_FABRIC_UUID_LEN as defined in nvml/nvml.h
	GPU_FABRIC_UUID_LEN = 16
	// GPU_FABRIC_STATE_NOT_SUPPORTED as defined in nvml/nvml.h
	GPU_FABRIC_STATE_NOT_SUPPORTED = 0
	// GPU_FABRIC_STATE_NOT_STARTED as defined in nvml/nvml.h
	GPU_FABRIC_STATE_NOT_STARTED = 1
	// GPU_FABRIC_STATE_IN_PROGRESS as defined in nvml/nvml.h
	GPU_FABRIC_STATE_IN_PROGRESS = 2
	// GPU_FABRIC_STATE_COMPLETED as defined in nvml/nvml.h
	GPU_FABRIC_STATE_COMPLETED = 3
	// GPU_FABRIC_HEALTH_MASK_DEGRADED_BW_NOT_SUPPORTED as defined in nvml/nvml.h
	GPU_FABRIC_HEALTH_MASK_DEGRADED_BW_NOT_SUPPORTED = 0
	// GPU_FABRIC_HEALTH_MASK_DEGRADED_BW_TRUE as defined in nvml/nvml.h
	GPU_FABRIC_HEALTH_MASK_DEGRADED_BW_TRUE = 1
	// GPU_FABRIC_HEALTH_MASK_DEGRADED_BW_FALSE as defined in nvml/nvml.h
	GPU_FABRIC_HEALTH_MASK_DEGRADED_BW_FALSE = 2
	// GPU_FABRIC_HEALTH_MASK_SHIFT_DEGRADED_BW as defined in nvml/nvml.h
	GPU_FABRIC_HEALTH_MASK_SHIFT_DEGRADED_BW = 0
	// GPU_FABRIC_HEALTH_MASK_WIDTH_DEGRADED_BW as defined in nvml/nvml.h
	GPU_FABRIC_HEALTH_MASK_WIDTH_DEGRADED_BW = 3
	// GPU_FABRIC_HEALTH_MASK_ROUTE_RECOVERY_NOT_SUPPORTED as defined in nvml/nvml.h
	GPU_FABRIC_HEALTH_MASK_ROUTE_RECOVERY_NOT_SUPPORTED = 0
	// GPU_FABRIC_HEALTH_MASK_ROUTE_RECOVERY_TRUE as defined in nvml/nvml.h
	GPU_FABRIC_HEALTH_MASK_ROUTE_RECOVERY_TRUE = 1
	// GPU_FABRIC_HEALTH_MASK_ROUTE_RECOVERY_FALSE as defined in nvml/nvml.h
	GPU_FABRIC_HEALTH_MASK_ROUTE_RECOVERY_FALSE = 2
	// GPU_FABRIC_HEALTH_MASK_SHIFT_ROUTE_RECOVERY as defined in nvml/nvml.h
	GPU_FABRIC_HEALTH_MASK_SHIFT_ROUTE_RECOVERY = 2
	// GPU_FABRIC_HEALTH_MASK_WIDTH_ROUTE_RECOVERY as defined in nvml/nvml.h
	GPU_FABRIC_HEALTH_MASK_WIDTH_ROUTE_RECOVERY = 3
	// GPU_FABRIC_HEALTH_MASK_ROUTE_UNHEALTHY_NOT_SUPPORTED as defined in nvml/nvml.h
	GPU_FABRIC_HEALTH_MASK_ROUTE_UNHEALTHY_NOT_SUPPORTED = 0
	// GPU_FABRIC_HEALTH_MASK_ROUTE_UNHEALTHY_TRUE as defined in nvml/nvml.h
	GPU_FABRIC_HEALTH_MASK_ROUTE_UNHEALTHY_TRUE = 1
	// GPU_FABRIC_HEALTH_MASK_ROUTE_UNHEALTHY_FALSE as defined in nvml/nvml.h
	GPU_FABRIC_HEALTH_MASK_ROUTE_UNHEALTHY_FALSE = 2
	// GPU_FABRIC_HEALTH_MASK_SHIFT_ROUTE_UNHEALTHY as defined in nvml/nvml.h
	GPU_FABRIC_HEALTH_MASK_SHIFT_ROUTE_UNHEALTHY = 4
	// GPU_FABRIC_HEALTH_MASK_WIDTH_ROUTE_UNHEALTHY as defined in nvml/nvml.h
	GPU_FABRIC_HEALTH_MASK_WIDTH_ROUTE_UNHEALTHY = 3
	// GPU_FABRIC_HEALTH_MASK_ACCESS_TIMEOUT_RECOVERY_NOT_SUPPORTED as defined in nvml/nvml.h
	GPU_FABRIC_HEALTH_MASK_ACCESS_TIMEOUT_RECOVERY_NOT_SUPPORTED = 0
	// GPU_FABRIC_HEALTH_MASK_ACCESS_TIMEOUT_RECOVERY_TRUE as defined in nvml/nvml.h
	GPU_FABRIC_HEALTH_MASK_ACCESS_TIMEOUT_RECOVERY_TRUE = 1
	// GPU_FABRIC_HEALTH_MASK_ACCESS_TIMEOUT_RECOVERY_FALSE as defined in nvml/nvml.h
	GPU_FABRIC_HEALTH_MASK_ACCESS_TIMEOUT_RECOVERY_FALSE = 2
	// GPU_FABRIC_HEALTH_MASK_SHIFT_ACCESS_TIMEOUT_RECOVERY as defined in nvml/nvml.h
	GPU_FABRIC_HEALTH_MASK_SHIFT_ACCESS_TIMEOUT_RECOVERY = 6
	// GPU_FABRIC_HEALTH_MASK_WIDTH_ACCESS_TIMEOUT_RECOVERY as defined in nvml/nvml.h
	GPU_FABRIC_HEALTH_MASK_WIDTH_ACCESS_TIMEOUT_RECOVERY = 3
	// GPU_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION_NOT_SUPPORTED as defined in nvml/nvml.h
	GPU_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION_NOT_SUPPORTED = 0
	// GPU_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION_NONE as defined in nvml/nvml.h
	GPU_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION_NONE = 1
	// GPU_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION_INCORRECT_SYSGUID as defined in nvml/nvml.h
	GPU_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION_INCORRECT_SYSGUID = 2
	// GPU_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION_INCORRECT_CHASSIS_SN as defined in nvml/nvml.h
	GPU_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION_INCORRECT_CHASSIS_SN = 3
	// GPU_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION_NO_PARTITION as defined in nvml/nvml.h
	GPU_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION_NO_PARTITION = 4
	// GPU_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION_INSUFFICIENT_NVLINKS as defined in nvml/nvml.h
	GPU_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION_INSUFFICIENT_NVLINKS = 5
	// GPU_FABRIC_HEALTH_MASK_SHIFT_INCORRECT_CONFIGURATION as defined in nvml/nvml.h
	GPU_FABRIC_HEALTH_MASK_SHIFT_INCORRECT_CONFIGURATION = 8
	// GPU_FABRIC_HEALTH_MASK_WIDTH_INCORRECT_CONFIGURATION as defined in nvml/nvml.h
	GPU_FABRIC_HEALTH_MASK_WIDTH_INCORRECT_CONFIGURATION = 15
	// GPU_FABRIC_HEALTH_SUMMARY_NOT_SUPPORTED as defined in nvml/nvml.h
	GPU_FABRIC_HEALTH_SUMMARY_NOT_SUPPORTED = 0
	// GPU_FABRIC_HEALTH_SUMMARY_HEALTHY as defined in nvml/nvml.h
	GPU_FABRIC_HEALTH_SUMMARY_HEALTHY = 1
	// GPU_FABRIC_HEALTH_SUMMARY_UNHEALTHY as defined in nvml/nvml.h
	GPU_FABRIC_HEALTH_SUMMARY_UNHEALTHY = 2
	// GPU_FABRIC_HEALTH_SUMMARY_LIMITED_CAPACITY as defined in nvml/nvml.h
	GPU_FABRIC_HEALTH_SUMMARY_LIMITED_CAPACITY = 3
	// INIT_FLAG_NO_GPUS as defined in nvml/nvml.h
	INIT_FLAG_NO_GPUS = 1
	// INIT_FLAG_NO_ATTACH as defined in nvml/nvml.h
	INIT_FLAG_NO_ATTACH = 2
	// DEVICE_INFOROM_VERSION_BUFFER_SIZE as defined in nvml/nvml.h
	DEVICE_INFOROM_VERSION_BUFFER_SIZE = 16
	// DEVICE_UUID_BUFFER_SIZE as defined in nvml/nvml.h
	DEVICE_UUID_BUFFER_SIZE = 80
	// DEVICE_UUID_V2_BUFFER_SIZE as defined in nvml/nvml.h
	DEVICE_UUID_V2_BUFFER_SIZE = 96
	// DEVICE_PART_NUMBER_BUFFER_SIZE as defined in nvml/nvml.h
	DEVICE_PART_NUMBER_BUFFER_SIZE = 80
	// SYSTEM_DRIVER_VERSION_BUFFER_SIZE as defined in nvml/nvml.h
	SYSTEM_DRIVER_VERSION_BUFFER_SIZE = 80
	// SYSTEM_NVML_VERSION_BUFFER_SIZE as defined in nvml/nvml.h
	SYSTEM_NVML_VERSION_BUFFER_SIZE = 80
	// DEVICE_NAME_BUFFER_SIZE as defined in nvml/nvml.h
	DEVICE_NAME_BUFFER_SIZE = 64
	// DEVICE_NAME_V2_BUFFER_SIZE as defined in nvml/nvml.h
	DEVICE_NAME_V2_BUFFER_SIZE = 96
	// DEVICE_SERIAL_BUFFER_SIZE as defined in nvml/nvml.h
	DEVICE_SERIAL_BUFFER_SIZE = 30
	// DEVICE_VBIOS_VERSION_BUFFER_SIZE as defined in nvml/nvml.h
	DEVICE_VBIOS_VERSION_BUFFER_SIZE = 32
	// AFFINITY_SCOPE_NODE as defined in nvml/nvml.h
	AFFINITY_SCOPE_NODE = 0
	// AFFINITY_SCOPE_SOCKET as defined in nvml/nvml.h
	AFFINITY_SCOPE_SOCKET = 1
	// NVLINK_BER_MANTISSA_SHIFT as defined in nvml/nvml.h
	NVLINK_BER_MANTISSA_SHIFT = 8
	// NVLINK_BER_MANTISSA_WIDTH as defined in nvml/nvml.h
	NVLINK_BER_MANTISSA_WIDTH = 15
	// NVLINK_BER_EXP_SHIFT as defined in nvml/nvml.h
	NVLINK_BER_EXP_SHIFT = 0
	// NVLINK_BER_EXP_WIDTH as defined in nvml/nvml.h
	NVLINK_BER_EXP_WIDTH = 255
	// NVLINK_STATE_INACTIVE as defined in nvml/nvml.h
	NVLINK_STATE_INACTIVE = 0
	// NVLINK_STATE_ACTIVE as defined in nvml/nvml.h
	NVLINK_STATE_ACTIVE = 1
	// NVLINK_STATE_SLEEP as defined in nvml/nvml.h
	NVLINK_STATE_SLEEP = 2
	// NVLINK_TOTAL_SUPPORTED_BW_MODES as defined in nvml/nvml.h
	NVLINK_TOTAL_SUPPORTED_BW_MODES = 23
	// NVLINK_FIRMWARE_UCODE_TYPE_MSE as defined in nvml/nvml.h
	NVLINK_FIRMWARE_UCODE_TYPE_MSE = 1
	// NVLINK_FIRMWARE_UCODE_TYPE_NETIR as defined in nvml/nvml.h
	NVLINK_FIRMWARE_UCODE_TYPE_NETIR = 2
	// NVLINK_FIRMWARE_UCODE_TYPE_NETIR_UPHY as defined in nvml/nvml.h
	NVLINK_FIRMWARE_UCODE_TYPE_NETIR_UPHY = 3
	// NVLINK_FIRMWARE_UCODE_TYPE_NETIR_CLN as defined in nvml/nvml.h
	NVLINK_FIRMWARE_UCODE_TYPE_NETIR_CLN = 4
	// NVLINK_FIRMWARE_UCODE_TYPE_NETIR_DLN as defined in nvml/nvml.h
	NVLINK_FIRMWARE_UCODE_TYPE_NETIR_DLN = 5
	// NVLINK_FIRMWARE_VERSION_LENGTH as defined in nvml/nvml.h
	NVLINK_FIRMWARE_VERSION_LENGTH = 100
	// PRM_DATA_MAX_SIZE as defined in nvml/nvml.h
	PRM_DATA_MAX_SIZE = 496
	// DEVICE_MIG_DISABLE as defined in nvml/nvml.h
	DEVICE_MIG_DISABLE = 0
	// DEVICE_MIG_ENABLE as defined in nvml/nvml.h
	DEVICE_MIG_ENABLE = 1
	// GPU_INSTANCE_PROFILE_1_SLICE as defined in nvml/nvml.h
	GPU_INSTANCE_PROFILE_1_SLICE = 0
	// GPU_INSTANCE_PROFILE_2_SLICE as defined in nvml/nvml.h
	GPU_INSTANCE_PROFILE_2_SLICE = 1
	// GPU_INSTANCE_PROFILE_3_SLICE as defined in nvml/nvml.h
	GPU_INSTANCE_PROFILE_3_SLICE = 2
	// GPU_INSTANCE_PROFILE_4_SLICE as defined in nvml/nvml.h
	GPU_INSTANCE_PROFILE_4_SLICE = 3
	// GPU_INSTANCE_PROFILE_7_SLICE as defined in nvml/nvml.h
	GPU_INSTANCE_PROFILE_7_SLICE = 4
	// GPU_INSTANCE_PROFILE_8_SLICE as defined in nvml/nvml.h
	GPU_INSTANCE_PROFILE_8_SLICE = 5
	// GPU_INSTANCE_PROFILE_6_SLICE as defined in nvml/nvml.h
	GPU_INSTANCE_PROFILE_6_SLICE = 6
	// GPU_INSTANCE_PROFILE_1_SLICE_REV1 as defined in nvml/nvml.h
	GPU_INSTANCE_PROFILE_1_SLICE_REV1 = 7
	// GPU_INSTANCE_PROFILE_2_SLICE_REV1 as defined in nvml/nvml.h
	GPU_INSTANCE_PROFILE_2_SLICE_REV1 = 8
	// GPU_INSTANCE_PROFILE_1_SLICE_REV2 as defined in nvml/nvml.h
	GPU_INSTANCE_PROFILE_1_SLICE_REV2 = 9
	// GPU_INSTANCE_PROFILE_1_SLICE_GFX as defined in nvml/nvml.h
	GPU_INSTANCE_PROFILE_1_SLICE_GFX = 10
	// GPU_INSTANCE_PROFILE_2_SLICE_GFX as defined in nvml/nvml.h
	GPU_INSTANCE_PROFILE_2_SLICE_GFX = 11
	// GPU_INSTANCE_PROFILE_4_SLICE_GFX as defined in nvml/nvml.h
	GPU_INSTANCE_PROFILE_4_SLICE_GFX = 12
	// GPU_INSTANCE_PROFILE_1_SLICE_NO_ME as defined in nvml/nvml.h
	GPU_INSTANCE_PROFILE_1_SLICE_NO_ME = 13
	// GPU_INSTANCE_PROFILE_2_SLICE_NO_ME as defined in nvml/nvml.h
	GPU_INSTANCE_PROFILE_2_SLICE_NO_ME = 14
	// GPU_INSTANCE_PROFILE_1_SLICE_ALL_ME as defined in nvml/nvml.h
	GPU_INSTANCE_PROFILE_1_SLICE_ALL_ME = 15
	// GPU_INSTANCE_PROFILE_2_SLICE_ALL_ME as defined in nvml/nvml.h
	GPU_INSTANCE_PROFILE_2_SLICE_ALL_ME = 16
	// GPU_INSTANCE_PROFILE_COUNT as defined in nvml/nvml.h
	GPU_INSTANCE_PROFILE_COUNT = 17
	// GPU_INSTANCE_PROFILE_CAPS_P2P as defined in nvml/nvml.h
	GPU_INSTANCE_PROFILE_CAPS_P2P = 1
	// GPU_INTSTANCE_PROFILE_CAPS_P2P as defined in nvml/nvml.h
	GPU_INTSTANCE_PROFILE_CAPS_P2P = 1
	// GPU_INSTANCE_PROFILE_CAPS_GFX as defined in nvml/nvml.h
	GPU_INSTANCE_PROFILE_CAPS_GFX = 2
	// COMPUTE_INSTANCE_PROFILE_CAPS_GFX as defined in nvml/nvml.h
	COMPUTE_INSTANCE_PROFILE_CAPS_GFX = 1
	// COMPUTE_INSTANCE_PROFILE_1_SLICE as defined in nvml/nvml.h
	COMPUTE_INSTANCE_PROFILE_1_SLICE = 0
	// COMPUTE_INSTANCE_PROFILE_2_SLICE as defined in nvml/nvml.h
	COMPUTE_INSTANCE_PROFILE_2_SLICE = 1
	// COMPUTE_INSTANCE_PROFILE_3_SLICE as defined in nvml/nvml.h
	COMPUTE_INSTANCE_PROFILE_3_SLICE = 2
	// COMPUTE_INSTANCE_PROFILE_4_SLICE as defined in nvml/nvml.h
	COMPUTE_INSTANCE_PROFILE_4_SLICE = 3
	// COMPUTE_INSTANCE_PROFILE_7_SLICE as defined in nvml/nvml.h
	COMPUTE_INSTANCE_PROFILE_7_SLICE = 4
	// COMPUTE_INSTANCE_PROFILE_8_SLICE as defined in nvml/nvml.h
	COMPUTE_INSTANCE_PROFILE_8_SLICE = 5
	// COMPUTE_INSTANCE_PROFILE_6_SLICE as defined in nvml/nvml.h
	COMPUTE_INSTANCE_PROFILE_6_SLICE = 6
	// COMPUTE_INSTANCE_PROFILE_1_SLICE_REV1 as defined in nvml/nvml.h
	COMPUTE_INSTANCE_PROFILE_1_SLICE_REV1 = 7
	// COMPUTE_INSTANCE_PROFILE_COUNT as defined in nvml/nvml.h
	COMPUTE_INSTANCE_PROFILE_COUNT = 8
	// COMPUTE_INSTANCE_ENGINE_PROFILE_SHARED as defined in nvml/nvml.h
	COMPUTE_INSTANCE_ENGINE_PROFILE_SHARED = 0
	// COMPUTE_INSTANCE_ENGINE_PROFILE_COUNT as defined in nvml/nvml.h
	COMPUTE_INSTANCE_ENGINE_PROFILE_COUNT = 1
	// GPM_METRICS_GET_VERSION as defined in nvml/nvml.h
	GPM_METRICS_GET_VERSION = 1
	// GPM_SUPPORT_VERSION as defined in nvml/nvml.h
	GPM_SUPPORT_VERSION = 1
	// DEV_CAP_EGM as defined in nvml/nvml.h
	DEV_CAP_EGM = 1
	// WORKLOAD_POWER_MAX_PROFILES as defined in nvml/nvml.h
	WORKLOAD_POWER_MAX_PROFILES = 255
	// POWER_SMOOTHING_MAX_NUM_PROFILES as defined in nvml/nvml.h
	POWER_SMOOTHING_MAX_NUM_PROFILES = 5
	// POWER_SMOOTHING_NUM_PROFILE_PARAMS as defined in nvml/nvml.h
	POWER_SMOOTHING_NUM_PROFILE_PARAMS = 4
	// POWER_SMOOTHING_ADMIN_OVERRIDE_NOT_SET as defined in nvml/nvml.h
	POWER_SMOOTHING_ADMIN_OVERRIDE_NOT_SET = 4294967295
	// POWER_SMOOTHING_PROFILE_PARAM_PERCENT_TMP_FLOOR as defined in nvml/nvml.h
	POWER_SMOOTHING_PROFILE_PARAM_PERCENT_TMP_FLOOR = 0
	// POWER_SMOOTHING_PROFILE_PARAM_RAMP_UP_RATE as defined in nvml/nvml.h
	POWER_SMOOTHING_PROFILE_PARAM_RAMP_UP_RATE = 1
	// POWER_SMOOTHING_PROFILE_PARAM_RAMP_DOWN_RATE as defined in nvml/nvml.h
	POWER_SMOOTHING_PROFILE_PARAM_RAMP_DOWN_RATE = 2
	// POWER_SMOOTHING_PROFILE_PARAM_RAMP_DOWN_HYSTERESIS as defined in nvml/nvml.h
	POWER_SMOOTHING_PROFILE_PARAM_RAMP_DOWN_HYSTERESIS = 3
)

const (
	SYSTEM_PROCESS_NAME_BUFFER_SIZE = 256
)