vivado

type Data struct {
	Key   string
	Value string
}

type PowerReport struct {
	EntityName      string  `json:"-"` //For identification, ignored when unmarshaling to JSON file
	TotalPower      float64 //W
	DynamicPower    float64 //W
	StaticPower     float64 //W
	ConfidenceLevel string  //High required
}

type Report struct {
	EntityName string
	Util       *Utilization
	Power      *PowerReport
	Timing     *Timing
	Other      []Data
}

type RptDoc struct {
	XMLName     xml.Name `xml:"RptDoc"`
	Text        string   `xml:",chardata"`
	Cmdline     string   `xml:"cmdline,attr"`
	Designname  string   `xml:"designname,attr"`
	Designstate string   `xml:"designstate,attr"`
	Partname    string   `xml:"partname,attr"`
	Speedfile   string   `xml:"speedfile,attr"`
	Title       string   `xml:"title,attr"`
	Version     string   `xml:"version,attr"`
	Section     []struct {
		Text  string `xml:",chardata"`
		Class string `xml:"class,attr"`
		Title string `xml:"title,attr"`
		Table struct {
			Text               string `xml:",chardata"`
			Class              string `xml:"class,attr"`
			Style              string `xml:"style,attr"`
			Title              string `xml:"title,attr"`
			UseFootnoteNumbers string `xml:"useFootnoteNumbers,attr"`
			Footnote           struct {
				Text     string `xml:",chardata"`
				AttrText string `xml:"text,attr"`
			} `xml:"footnote"`
			Tablerow []struct {
				Text           string `xml:",chardata"`
				Class          string `xml:"class,attr"`
				Suppressoutput string `xml:"suppressoutput,attr"`
				Wordwrap       string `xml:"wordwrap,attr"`
				Tablecell      []struct {
					Text     string `xml:",chardata"`
					Class    string `xml:"class,attr"`
					Contents string `xml:"contents,attr"`
					Halign   string `xml:"halign,attr"`
					Type     string `xml:"type,attr"`
				} `xml:"tablecell"`
			} `xml:"tablerow"`
		} `xml:"table"`
		Section []struct {
			Text  string `xml:",chardata"`
			Class string `xml:"class,attr"`
			Title string `xml:"title,attr"`
			Table struct {
				Text               string `xml:",chardata"`
				Class              string `xml:"class,attr"`
				Style              string `xml:"style,attr"`
				Title              string `xml:"title,attr"`
				UseFootnoteNumbers string `xml:"useFootnoteNumbers,attr"`
				Tablerow           []struct {
					Text           string `xml:",chardata"`
					Class          string `xml:"class,attr"`
					Suppressoutput string `xml:"suppressoutput,attr"`
					Wordwrap       string `xml:"wordwrap,attr"`
					Tableheader    []struct {
						Text     string `xml:",chardata"`
						Class    string `xml:"class,attr"`
						Contents string `xml:"contents,attr"`
						Halign   string `xml:"halign,attr"`
						Width    string `xml:"width,attr"`
					} `xml:"tableheader"`
					Tablecell []struct {
						Text          string `xml:",chardata"`
						Class         string `xml:"class,attr"`
						Contents      string `xml:"contents,attr"`
						Halign        string `xml:"halign,attr"`
						Type          string `xml:"type,attr"`
						Decimalplaces string `xml:"decimalplaces,attr"`
					} `xml:"tablecell"`
				} `xml:"tablerow"`
			} `xml:"table"`
		} `xml:"section"`
	} `xml:"section"`
}

type Run struct {
	Name       string
	Reports    []Report
	ResultPath string `json:"-"`
	ReportPath string `json:"-"`
	Other      []Data
}

type Timing struct {
	EntityName string `json:"-"` //For identification, ignored when unmarshaling to JSON file
	EndPoint   string
	WorstPath  float64 //ns
	MaxFreq    float64 //MHz
}

type Utilization struct {
	EntityName string `json:"-"` //For identification, ignored when unmarshaling to JSON file
	TotalLUT   int
	LogicLUT   int
	LUTRAMs    int
	SRLs       int
	FFs        int
	RAMB36     int
	RAMB18     int
	DSP        int
	CARRY      int
}

type VivadoTCL struct {
	FolderPath string
	TopName    string
	FileName   string
	Settings   *VivadoTCLSettings
}

type VivadoTCLSettings struct {
	PartName        string
	OOC             bool // Enables Out-of-Context synthesis
	NODSP           bool // When TRUE disables the use of DSP slices for the synthesis of the design
	WriteCheckpoint bool // Enables exporting Checkpoints after synthesis and place+route
	Placement       bool // Enables Placement
	Route           bool // Enables Routing
	Funcsim         bool // Note: Set to false to disable funcsim VHDL file for post-processing.
	Utilization     bool // Enables Exporting of Utilization Report
	Hierarchical    bool // Enables Hierachical Utilization Report //Note: Setting this to false, does break utilization report parsing
	Clk             bool // Set this flag to TRUE if the design has a clock, else potentially breaking
	Timing          bool
}

type XSIM struct {
	SimFile       string //Points to TestBench File
	TopFile       string //Points to TopLevel VHDL file
	TestFile      string //Points to TestData used for XSIM Simulation
	TopEntityName string //TopLevel EntityName
	FolderPath    string
	TemplateFile  string            //Points to Template for TestBench File
	VHDLEntities  []VHDL.VHDLEntity //Array of VHDLEntities (generated by GenerateVHDLEntityArray())
	BitSize       uint
	OutputSize    uint
	ScaleN        uint // How many entities are being simulated, used if Scaler model
	PostSim       bool // True for PostSim, used for power simulation
}