Documentation
¶
Overview ¶
Package dma provides interface to the DMA controller. The interface is based on two main types: Controller and Channel.
Controller represents an instance of DMA controller (RP2350 provides only one controller numbered as 0). Each controller provides 16 channels.
Channel represents a DMA channel. As all available channels have identical functionality this package doesn't allow you to select a specific channel. Instead you can use Controller.AllocChannel to allocate an unused one.
Index ¶
- Constants
- func AlignOffsets(ptr unsafe.Pointer, size uintptr) (start, end uintptr)
- func MakeSlice[T any](len, cap int) (slice []T)
- func New[T any]() (ptr *T)
- type Channel
- func (c Channel) Clear(status uint8)
- func (c Channel) ClearIRQ()
- func (c Channel) ClearTrig(status uint8)
- func (c Channel) Config() (cfg Config, chainTo Channel)
- func (c Channel) Controller() *Controller
- func (c Channel) DisableIRQ(irqn int)
- func (c Channel) EnableIRQ(irqn int)
- func (c Channel) Free()
- func (c Channel) IRQEnabled(irqn int) bool
- func (c Channel) IsActiveIRQ(irqn int) bool
- func (c Channel) IsIRQ() bool
- func (c Channel) IsValid() bool
- func (c Channel) Num() int
- func (c Channel) ReadAddr() uintptr
- func (c Channel) SetConfig(cfg Config, chainTo Channel)
- func (c Channel) SetConfigTrig(cfg Config, chainTo Channel)
- func (c Channel) SetReadAddr(a unsafe.Pointer)
- func (c Channel) SetReadAddrTrig(a unsafe.Pointer)
- func (c Channel) SetTransCount(cnt int, mode int8)
- func (c Channel) SetTransCountTrig(cnt int, mode int8)
- func (c Channel) SetWriteAddr(a unsafe.Pointer)
- func (c Channel) SetWriteAddrTrig(a unsafe.Pointer)
- func (c Channel) Status() uint8
- func (c Channel) TransCount() (cnt int, mode int8)
- func (c Channel) Trig()
- func (c Channel) WriteAddr() uintptr
- type Config
- type Controller
- func (d *Controller) ActiveIRQs(irqn int) uint32
- func (d *Controller) AllocChannel() (ch Channel)
- func (d *Controller) ClearIRQs(irqs uint32)
- func (d *Controller) DisableIRQs(irqn int, channels uint32)
- func (d *Controller) EnableIRQs(irqn int, channels uint32)
- func (d *Controller) IRQs() uint32
- func (d *Controller) IRQsEnabled(irqn int) uint32
- func (d *Controller) Trig(channels uint32)
Constants ¶
const ( Normal int8 = 0 // normal mode, compatible with the RP2040 TriggerSelf int8 = 1 // re-triggers itself at the end of transfer Endless int8 = 15 // perform an endless sequence of transfers )
Transfer counter mode
const ( Busy uint8 = 1 << 0 // The channel performs transfer WriteErr uint8 = 1 << 3 // Write bus error (use Clear to clear) ReadErr uint8 = 1 << 4 // Read bus error ( AHBErr uint8 = 1 << 5 // Logical OR of the WriteErr and ReadErr flags )
Status
const CacheMaint bool = cacheMaint
A CacheMaint indicates whether DMA requires cache maintenance.
const MemAlign = cacheLineSize
An MemAlign is the prefered memory alignment for DMA operations. It's always power of 2 and defined in such a way that a fully MemAlign aligned (top and bottom) memory region corresponds to the complete data cache lines.
Variables ¶
This section is empty.
Functions ¶
func AlignOffsets ¶
AlignOffsets calculatest the start and end offsets to the MemAlign aligned portion of the memory described by ptr and size.
Types ¶
type Channel ¶
type Channel struct {
// contains filtered or unexported fields
}
Channel rperesents a DMA channel.
func (Channel) Clear ¶
Clear clears the selected status bits. Only WriteErr and ReadErr bits an be cleard this way.
func (Channel) ClearIRQ ¶
func (c Channel) ClearIRQ()
ClearIRQ clears the interrupr request for this channel.
func (Channel) Controller ¶
func (c Channel) Controller() *Controller
Controller returns the controller that the channel belongs to.
func (Channel) DisableIRQ ¶
DisableIRQ disables routing the interrupts from this DMA channel to the system-level DMA interrupt line irqn.
func (Channel) EnableIRQ ¶
EnableIRQ enables routing the interrupts from this DMA channel to the system-level DMA interrupt line irqn.
func (Channel) Free ¶
func (c Channel) Free()
Free frees the channel so the Controller.AllocChannel can allocate it next time.
func (Channel) IRQEnabled ¶
IRQEnabled reports whether the the interrupts from this DMA channel are routed to the system-level DMA interrupt line irqn.
func (Channel) IsActiveIRQ ¶
IsActiveIRQ reports whether the current DMA interrupt state causes the interrupt request on the system-level DMA interrupt line irqn.
func (Channel) IsIRQ ¶
IsIRQ reports the interrupt status for the channel regardless of whether it causes any system-level DMA interrupt.
func (Channel) IsValid ¶
IsValid reports whether the channel is valid, e.g. succesfully allocated by the Controller.AllocChannel method.
func (Channel) SetConfig ¶
SetConfig configures the channel c according to the cfg with the chainTo channel to be triggered at the end of transfer. Set chainTo to Channel{} or c (chain to itself) to disable chaining.
func (Channel) SetConfigTrig ¶
SetConfigTrig is like SetConfig but also triggers the transfer.
func (Channel) SetReadAddr ¶
func (Channel) SetReadAddrTrig ¶
func (Channel) SetTransCount ¶
SetTransCount sets the transfer counter and mode.
func (Channel) SetTransCountTrig ¶
SetTransCountTrig is like SetTransCount but also triggers the transfer.
func (Channel) SetWriteAddr ¶
func (Channel) SetWriteAddrTrig ¶
func (Channel) TransCount ¶
TransCount return the current transfer counter and mode.
type Config ¶
type Config uint32
Config represents the channel configuration.
const ( En Config = 1 << 0 // DMA channel enable PrioH Config = 1 << 1 // Referential treatment in issue scheduling DataSize Config = 3 << 2 // Size of each bus transfer: S8b Config = 0 << 2 // - byte S16b Config = 1 << 2 // - half word S32b Config = 2 << 2 // - word IncR Config = 1 << 4 // Increment read address with each transfer RevR Config = 1 << 5 // Decrement read address rather than increment IncW Config = 1 << 6 // Increment write address with each transfer RevW Config = 1 << 7 // Decrement write address rather than increment RingW Config = 1 << 12 // Apply RingSize to write instead of read TransReq Config = 0x3F << 17 // Select a Transfer Request signal: PIO0_TX0 Config = 0x00 << 17 // - PIO0's TX FIFO 0 PIO0_TX1 Config = 0x01 << 17 // - PIO0's TX FIFO 1 PIO0_TX2 Config = 0x02 << 17 // - PIO0's TX FIFO 2 PIO0_TX3 Config = 0x03 << 17 // - PIO0's TX FIFO 3 PIO0_RX0 Config = 0x04 << 17 // - PIO0's RX FIFO 0 PIO0_RX1 Config = 0x05 << 17 // - PIO0's RX FIFO 1 PIO0_RX2 Config = 0x06 << 17 // - PIO0's RX FIFO 2 PIO0_RX3 Config = 0x07 << 17 // - PIO0's RX FIFO 3 PIO1_TX0 Config = 0x08 << 17 // - PIO1's TX FIFO 0 PIO1_TX1 Config = 0x09 << 17 // - PIO1's TX FIFO 1 PIO1_TX2 Config = 0x0A << 17 // - PIO1's TX FIFO 2 PIO1_TX3 Config = 0x0B << 17 // - PIO1's TX FIFO 3 PIO1_RX0 Config = 0x0C << 17 // - PIO1's RX FIFO 0 PIO1_RX1 Config = 0x0D << 17 // - PIO1's RX FIFO 1 PIO1_RX2 Config = 0x0E << 17 // - PIO1's RX FIFO 2 PIO1_RX3 Config = 0x0F << 17 // - PIO1's RX FIFO 3 PIO2_TX0 Config = 0x10 << 17 // - PIO2's TX FIFO 0 PIO2_TX1 Config = 0x11 << 17 // - PIO2's TX FIFO 1 PIO2_TX2 Config = 0x12 << 17 // - PIO2's TX FIFO 2 PIO2_TX3 Config = 0x13 << 17 // - PIO2's TX FIFO 3 PIO2_RX0 Config = 0x14 << 17 // - PIO2's RX FIFO 0 PIO2_RX1 Config = 0x15 << 17 // - PIO2's RX FIFO 1 PIO2_RX2 Config = 0x16 << 17 // - PIO2's RX FIFO 2 PIO2_RX3 Config = 0x17 << 17 // - PIO2's RX FIFO 3 SPI0_TX Config = 0x18 << 17 // - SPI0's TX FIFO SPI0_RX Config = 0x19 << 17 // - SPI0's RX FIFO SPI1_TX Config = 0x1A << 17 // - SPI1's TX FIFO SPI1_RX Config = 0x1B << 17 // - SPI1's RX FIFO UART0_TX Config = 0x1C << 17 // - UART0's TX FIFO UART0_RX Config = 0x1D << 17 // - UART0's RX FIFO UART1_TX Config = 0x1E << 17 // - UART1's TX FIFO UART1_RX Config = 0x1F << 17 // - UART1's RX FIFO PWM_WRAP0 Config = 0x20 << 17 // - PWM Counter 0's Wrap Value PWM_WRAP1 Config = 0x21 << 17 // - PWM Counter 1's Wrap Value PWM_WRAP2 Config = 0x22 << 17 // - PWM Counter 2's Wrap Value PWM_WRAP3 Config = 0x23 << 17 // - PWM Counter 3's Wrap Value PWM_WRAP4 Config = 0x24 << 17 // - PWM Counter 4's Wrap Value PWM_WRAP5 Config = 0x25 << 17 // - PWM Counter 5's Wrap Value PWM_WRAP6 Config = 0x26 << 17 // - PWM Counter 6's Wrap Value PWM_WRAP7 Config = 0x27 << 17 // - PWM Counter 7's Wrap Value PWM_WRAP8 Config = 0x28 << 17 // - PWM Counter 8's Wrap Value PWM_WRAP9 Config = 0x29 << 17 // - PWM Counter 9's Wrap Value PWM_WRAP10 Config = 0x2A << 17 // - PWM Counter 0's Wrap Value PWM_WRAP11 Config = 0x2B << 17 // - PWM Counter 1's Wrap Value I2C0_TX Config = 0x2C << 17 // - I2C0's TX FIFO I2C0_RX Config = 0x2D << 17 // - I2C0's RX FIFO I2C1_TX Config = 0x2E << 17 // - I2C1's TX FIFO I2C1_RX Config = 0x2F << 17 // - I2C1's RX FIFO ADC Config = 0x30 << 17 // - the ADC XIP_STREAM Config = 0x31 << 17 // - the XIP Streaming FIFO XIP_QMITX Config = 0x32 << 17 // - XIP_QMITX XIP_QMIRX Config = 0x33 << 17 // - XIP_QMIRX HSTX Config = 0x34 << 17 // - HSTX CORESIGHT Config = 0x35 << 17 // - CORESIGHT SHA256 Config = 0x36 << 17 // - SHA256 TIMER0 Config = 0x3B << 17 // - Timer 0 TIMER1 Config = 0x3C << 17 // - Timer 1 TIMER2 Config = 0x3D << 17 // - Timer 2 (Optional) TIMER3 Config = 0x3E << 17 // - Timer 3 (Optional) Always Config = 0x3F << 17 // - permanent request Quiet Config = 1 << 23 // IRQ only when zero/null written to trig register Swap Config = 1 << 24 // Reverse the order of bytes in the transfered word SnifEn Config = 1 << 25 // Transfers are visible to the sniff hardware )
type Controller ¶
type Controller struct {
// contains filtered or unexported fields
}
A Controller represents a DMA controller.
func DMA ¶
func DMA(n int) *Controller
DMA returns n-th controller (RP2350 suports onlu conrtoller 0).
func (*Controller) ActiveIRQs ¶
func (d *Controller) ActiveIRQs(irqn int) uint32
ActiveIRQs returns the bitmask that represents the channels that cause the system-level DMA interrupt irqn.
func (*Controller) AllocChannel ¶
func (d *Controller) AllocChannel() (ch Channel)
AllocChannel allocates a free channel in the controller. It returns an invalid channel if there is no free channel to be allocated. Use Channel.Free to free an unused channel.
func (*Controller) ClearIRQs ¶
func (d *Controller) ClearIRQs(irqs uint32)
ClearIRQs clears the interrupts for the channels specified by bitmask.
func (*Controller) DisableIRQs ¶
func (d *Controller) DisableIRQs(irqn int, channels uint32)
DisableIRQs disables routing the interrupts from the specified DMA channels to the system-level DMA interrupt line irqn.
func (*Controller) EnableIRQs ¶
func (d *Controller) EnableIRQs(irqn int, channels uint32)
EnableIRQs enables routing the interrupts from the specified DMA channels to the system-level DMA interrupt line irqn.
func (*Controller) IRQs ¶
func (d *Controller) IRQs() uint32
IRQs returns the bitmask that represents the interrupt status for all channels regardless of whether theay cause any system-level DMA interrupt.
func (*Controller) IRQsEnabled ¶
func (d *Controller) IRQsEnabled(irqn int) uint32
IRQsEnabled returns the bitmask that represents the DMA channels which interrupts are routed to the system-level DMA interrupt line irqn.
func (*Controller) Trig ¶
func (d *Controller) Trig(channels uint32)
Trig triggers the transfers on channels specified by the channels bitmask.
Source Files
Directories
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Package dmairq allows to share the limited number of system-level DMA interrupts between the interrupt service routines (ISRs, interrupt hadlers) for individual DMA channels.
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Package dmairq allows to share the limited number of system-level DMA interrupts between the interrupt service routines (ISRs, interrupt hadlers) for individual DMA channels. |