Documentation
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Overview ¶
Headless go-virtio validate harness: boots tamago/amd64 under QEMU, drives a real virtio-gpu-pci device through the go-virtio/gpu 2D framebuffer driver, renders a soft3d cube into the framebuffer, flushes it to the host scanout, and reports a pixel checksum over the serial console. The screendump-based pixel validation is performed by the host harness (run.sh) against the QEMU monitor.
NOTE: an earlier version of this harness capped the framebuffer at 96x72 because the guest appeared to "#DF after a fixed compute budget" under QEMU TCG. That was a misdiagnosis: it was not a CPU double fault but the legacy 8259 PIT (IRQ0) firing on IDT vector 8 (the #DF slot) because the board never masked the legacy PIC while routing through the I/O APIC. The board now masks the PIC (board.Init: outb(0x21, 0xff)), so sustained compute is safe and the framebuffer runs at full resolution.
tamagoTransport bridges go-virtio/common.Transport to tamago's amd64 PCI + DMA facilities so the transport-agnostic virtio-gpu driver can drive a real virtio-gpu-pci device under QEMU.
Three sub-interfaces (see go-virtio/common/transport.go):
PCIConfigReader: routed to tamago's soc/intel/pci.Device, which performs port-mapped (0xcf8/0xcfc) PCI configuration-space reads.
BARMemoryAccessor: routed to direct MMIO. tamago's amd64 init.s identity-maps the full 32-bit space plus a 2 GiB 64-bit window (0x100000000..0x17fffffff), with the PCI MMIO hole (0xc0000000..0xffffffff) and the 64-bit window mapped uncacheable. A virtio BAR therefore resolves to a plain physical address we read and write through an unsafe.Pointer.
PageAllocator: routed to tamago's dma.Reserve, which carves page-aligned, physically-contiguous, identity-mapped buffers out of the board's global DMA region.